Conventional computing architectures are poor suited to the unique workload demands of deep learning, which has led to a surge in interest in memory-centric computing. Herein, a trilayer (Hf0.8Si0.2O2/Al2O3/Hf0.5Si0.5O2)-based self-rectifying resistive memory cell (SRMC) that exhibits (i) large selectivity (ca. 104), (ii) two-bit operation, (iii) low read power (4 and 0.8 nW for low and high resistance states, respectively), (iv) read latency (<10 μs), (v) excellent non-volatility (data retention >104 s at 85 °C), and (vi) complementary metal-oxide-semiconductor compatibility (maximum supply voltage ≤5 V) is introduced, which outperforms previously reported SRMCs. These characteristics render the SRMC highly suitable for the main memory for memory-centric computing which can improve deep learning acceleration. Furthermore, the low programming power (ca. 18 nW), latency (100 μs), and endurance (>106) highlight the energy-efficiency and highly reliable random-access memory of our SRMC. The feasible operation of individual SRMCs in passive crossbar arrays of different sizes (30 × 30, 160 × 160, and 320 × 320) is attributed to the large asymmetry and nonlinearity in the current-voltage behavior of the proposed SRMC, verifying its potential for application in large-scale and high-density non-volatile memory for memory-centric computing.
In this study, highly reliable and accurate weight‐modification behaviors are realized using a W/Al2O3 (3 nm)/HfO2 (7 nm)/TiN memristive device. The accuracy of the simulated inference of the MNIST dataset when considering the weight‐modification behavior is ≈95%. It is determined the optimal programming voltage pulsing conditions considering i) a high linearity in the weight‐modification, ii) symmetry between potentiation and depression, and iii) an alleviation of the voltage‐driving circuit overhead for the related part of weight‐modification process. Particular emphasis is placed on the last concern, and thus, the fixed shape of each programming pulse for both potentiation and depression are utilized. The optimal pulse design is 500 µs for the pulse rising, plateau, and falling times and a 2 V amplitude at the absolute scale. Additionally, the nonparametric method to evaluate the linearity and symmetry as opposed to the application of several parametric methods are proposed. The nonparametric method is based on an evaluation of actual data rather than models, and thus considers the actual variability in the conductance change, which is otherwise often ignored in the parameter optimization process.
unit between vector matrices, the workload of MAC with high-dimensional vector matrices increases exponentially. [4,5] Alternatively, the process-in-memory (PIM) unit, a concept inspired by the human brain, outperforms the von Neumann computing system in unstructured data processing considering it can provide a parallel MAC operation and reduces the time of the data bus between the CPU and the memory.A crossbar array (CA) type device is the most suitable and intuitive structure to achieve the PIM owing to its complex parallel connection of unit memory cells in the CA. [6][7][8] On applying the input signal (voltage bias) to the CA, the output signal (current, input voltage (V) × unit cell conductance (S)) is obtained instantly and simultaneously through each output line by Kirchhoff's law. [9,10] Owing to this "instant and simultaneous" calculation method, the CA-based PIM outperforms the serial process based von-Neumann computing in terms of the operation energy and time. Additionally, the CAbased PIM exhibits an immune response in the MAC operation with vector matrix expansion, which is suitable for processing large amounts of unstructured data.A data storage unit in the CA-based PIM should simultaneously exhibit two types of characteristics: 1) Highly reliable and low-power memory device and 2) device for selection function to suppress the interference effect from the parallel-connected neighboring cells in the CA. Various non-volatile memory devices, such as ferroelectric random access memory (FRAM), phase-change random access memory (PRAM), spin-torquetransfer magnetic random access memory (STT-MRAM), and resistive switching random access memory (RRAM) have been considered for use as a memory element. [11][12][13][14][15][16][17][18][19][20][21][22] Among these devices, the RRAM exhibits outstanding characteristics, such as device scaling down, low power consumption, fast operation speed, simple structure, and high reliability.Various selection devices (SD) such as diodes, [23,24] metalinsulator-transition (MIT) devices, [25,26] ovonic threshold switch (OTS), [27][28][29] mixed-ionic-electronic-conductor (MIEC), [30,31] tunneling-oxide-based devices, [32,33] and timing selector [34] have been proposed to add the selection function to the RRAM devices. Furthermore, a 1-transistor and 1-resistor (1T1R) has been proposed as an active unit cell. [35][36][37] However, stacking SD with RRAM can cause various practical issues. First, tailoring Reducing computational complexity is essential in future computing systems for processing a large amount of unstructured data simultaneously. Dot-product operations using crossbar array devices have attracted considerable attention owing to their simple device structure, intuitive operation scheme, and high computational efficiency of parallel operation. The resistive switching device is considered a promising candidate as the main data storage in the crossbar array owing to its highly reliable performance. In this study, a tri-layer TaO x /Al 2 O 3 /Ti:SiO x -based resistive...
Fully “Erase-free” multi-bit operation was demonstrated in a W/HfO2/TiN-stacked resistive switching device. The term Erase-free means that a digital state in a multi-bit operation can be achieved without initializing the device resistance state when the device moves to another digital state. Because initializing the resistance state of a resistive switching device causes high energy consumption, omitting this sequence can achieve energy efficient multi-bit operation during rewriting of the resistance state of the device. Experimentally, an operational energy savings of up to 75% was confirmed. For stable and reliable Erase-free operation, several prerequisites are required, such as gradual resistance change with electric pulse stimuli during both writing and erasing, predictable operational voltages for certain resistance states, and high reliability of resistive switching. These prerequisites could be achieved by adopting a W top electrode in a W/HfO2/TiN-stacked resistive switching device. These results can pave the way to future nonvolatile memory applications.
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