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This paper studies the integration of data compression into block devices built upon non-volatile memory (NVM). Although byteaddressable NVM-based main memory systems received most attention from the research community, industry chose to first commercialize NVM-based block devices, at least partly because block devices can much better mitigate non-ideal NVM characteristics (e.g., random bit errors, wear-out, and defects). It is very likely that NVMbased memory and block devices will co-exist in future computing systems, complementing to DRAM and flash memory. Compared with their flash-based counterparts, NVM-based block devices have shorter read latency but suffer from higher cost. Although data compression can reduce storage cost, conventional wisdom suggests that data compression inevitably degrades the access latency. Hence one may intuitively conclude that NVM-based block devices with built-in data compression must trade latency for bit cost. This paper shows that such an intuitive conclusion is not necessarily true. In particular, this paper presents a set of architectural design techniques that can reduce the read latency of NVM-based block devices with built-in data compression. Simulation results show that, compared with NVM-based block devices without built-in data compression, we can significantly reduce the read latency (e.g., by even more than 90%) without compromising the capability of tolerating non-ideal NVM characteristics.

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