Near-threshold voltage (Vth) operation is an effective method for lowering energy consumption. However, it increases the impact of Vth variation significantly, which makes it difficult for previously proposed static random access memory (SRAM) bitcells to achieve high read stability and write ability yields. To achieve these in the near-Vth region, a differential 7T SRAM bitcell is proposed in which an additional row-based control signal and an nMOS transistor between the pull-up and pull-down transistors is adopted on one side of the cross-coupled inverter. In addition, the proposed SRAM bitcell can use a bit-interleaved structure without the half-select issue. Compared to differential 10T and 12T SRAM, the proposed differential 7T SRAM achieves 5% and 6% higher SRAM operating frequency and 70% and 23% lower operation energy consumption with a 33% and 49% smaller bitcell area, respectively.INDEX TERMS 7T bitcell, half-select issue, low energy consumption, near-threshold voltage, static random access memory (SRAM).

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