Li+ electrolyte-gated transistors (EGTs) have attracted significant attention as artificial synapses because of the fast response of Li+ ion, low operating voltage, and applicability to flexible electronics. Due to the inherent nature of Li+ ion, Li+ EGTs show, however, limitations, such as poor long-term synaptic plasticity and nonlinear/nonsymmetric conductance update, which hinder the practical applications of artificial synapses. Herein, Li+ EGTs integrated with poly(vinylidene fluoride-co-trifluoroethylene) (PVDF-TrFE) ferroelectric polymer as a channel–electrolyte interlayer are presented. Owing to the polarized domains of PVDF-TrFE, the transport of Li+ ions at the channel–electrolyte interface is accelerated, and Li+ ions effectively penetrate the channel. Moreover, the self-diffusion of Li+ ions from the channel to the electrolyte is suppressed by the downward polarized domains. Li+ EGTs, therefore, successfully demonstrate synaptic characteristics, including excitatory postsynaptic current, short-/long-term synaptic plasticity, and paired-pulse facilitation. Also, conductance update in Li+ EGTs shows a dynamic range ( Gmax/ Gmin) of 92.42, high linearity, and distinct stability over 100 cycles. Based on their synaptic characteristics, inference simulations using a convolution neural network for the CIFAR-10 dataset imply that Li+ EGTs are suitable as artificial synapses with an inference accuracy of 89.13%. The new methodological approach addressing modulation of ion dynamics at the interface is introduced for developing practical synaptic devices.

Cuprous oxide (Cu2O) p-type thin-film transistors (TFTs) can be practically applied for complementary metal oxide semiconductor (CMOS) logic circuits, but the electrical performances are still insufficient due to high off-current and low field-effect mobility. Here, we have demonstrated Cu2O TFTs with improved field-effect mobility and low off-current through reduction of cupric oxide (CuO) impurities and dissociative Cu defects with the combination of deposition and annealing conditions. Copper oxide was deposited by radio frequency sputtering in mixed gases of argon and oxygen. After that, the deposited copper oxide was annealed at 800 °C in the tube furnace under a N2 atmosphere instead of a high vacuum condition. The fabricated Cu2O thin film had a high crystalline quality, the ratio of dissociative Cu defects decreased from 11.3 to 3.1%, and the electrical performances of the TFT including the fabricated Cu2O thin film exhibited the field-effect mobility of 1.11 ± 0.05 cm2/V·s, the on/off current ratio of 4.68 ± 0.8 × 104, and the subthreshold swing value of 3.91 ± 0.21 V dec–1. The fabricated Cu2O TFT showed a Vth shift of 3.31 V in the transfer curve under negative bias stress. Nitrogen plays a role in promoting Cu2O phase formation while it prevents CuO phase formation during the annealing process. In addition, oxygen added during sputtering increases the ratio of CuO in the copper oxide thin film and works effectively to reduce dissociative Cu defects in the annealing process. To determine the feasibility of the CMOS logic circuit, we also demonstrated the inverter with n-type indium–gallium–zinc oxide (IGZO) TFT and p-type Cu2O TFT, which showed a voltage gain of 14 at V DD = 20 V.

Synaptic devices that mimic biological neurons have attracted much attention for brain-inspired neuromorphic computing. Especially, synaptic thin-film transistors (TFTs) have emerged with simultaneous signal processing and information storage advantages. However, the analysis of excitatory postsynaptic current (EPSC) relies on an empirical model such as a serial RC circuit, which limits a systematic and in-depth study of synaptic devices in terms of material and electrical properties. Herein, the single-pulse-driven synaptic EPSC (SPSE) model, including capacitive effect and information of the synaptic window, is analytically proposed. The SPSE model can simulate EPSC of synaptic devices at given TFT-operating conditions. EPSC with the SPSE model can be characterized with quantified parameters for the capacitive effects and the synaptic windows, which also depend on the electrical condition applied to TFTs. Various kinds of synaptic-TFTs with different gate insulators (e.g., SiO2 and ion-gel) are used to confirm the performance of the SPSE model. For example, the SPSE model can capture the long-term robustness of ion-gel-based TFTs with specific quantified parameters. In addition, the SPSE model enables the estimation of energy consumption, which can potentially be leveraged to compare the energy cost of EPSC fairly. The SPSE model can provide a guideline to understand the physical properties of synaptic TFTs.