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A method for designing delay-insensitive circuits is presented based on a simple formalism. The communication behavior of a circuit with Its envlronmenf is speclfied by a regular expresslon-llke program. Based on formal manipulations this program is then transformed into a delay·insensltlve connection of basic elements realizing the specified circuit. The notion 01 delay-lnsensitlvlty Is concisely formalized.

A technique is presented to predict the performance behavior of control circuits for a linear FIFO. The control circuit consists of a linear chain of RendezVous elements, also called JOINs, preceded by a source and followed by a sink. The technique predicts how the cycle time, or throughput, of the FIFO depends on the sink delay, the source delay, and the length of the FIFO. It also predicts how the delays in each RendezVous element depend on the same set of parameters. The pipelines can be divided into three cases: sourcelimited, sink-limited, and self-limited pipelines. The technique is based on the assumption that the delays through a RendezVous element can be described as a function of the separation in arrival times of the inputs. Such descriptions are conveniently represented by the so-called Charlie diagram.

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