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Abstract. In this paper, we present a framework where a learning rule can be optimized within a parametric learning rule space. We define what we call parametric learning rules and present a theoretical study of their generalization properties when estimated from a set of learning tasks and tested over another set of tasks. We corroborate the results of this study with practical experiments.

We present in this paper the architecture and implementation of the Virtual Image Processor (VIP) which is an SIMD multiprocessor build with large FPGAs.The SIMD architecture, together with a 2D torus connection topology, is well suited for image processing, pattern recognition and neural network algorithms. The VIP board can be programmed on-line at the logic level, allowing optimal hardware dedication to any given algorithm. 1: IntroductionEven with the last decades exponential growth in performance of integrated circuits, many image processing and neural network applications still demand increased hardware speed. A first approach to increase performance is to build massively parallel computers. Their high price and difficulty to program have resulted in a very low acceptance rate. The design cycle of those computers is usually too long, and thus their technology is obsolete before they are commercially available. Consequently, users often prefer to use the latest high performance general workstation that is much less expensive and more easy to program. A second approach to solve the performance problem is to design dedicated parallel hardware for one task (or set of similar tasks). Their programmation is usually simple (or even nonexistent) while their performance/cost ratio is high. However, they are not flexible and their design cycle is long.Over the last few years, advances in programmable logic devices have resulted in the commercialization of field programmable gate arrays (FPGA) which allow to put large numbers of programmable logic elements on a single chip. The size and speed of those circuits improve at the same rate as microprocessors' size and speed, since they rely on the same technology. In section 2, we propose an architectural framework for the virtual image processor (VIP) which is a parallel processor having large FPGAs as main components. In section 3, we present the first prototype of the VIP board that uses 5 large FPGAs, has 1.5 MB of static RAM and communicates through a fast PCI bus.We are currently targeting at applications requiring a large number of simple low precision operations. Many commercially attractive applications fall into this category such as image processing and pattern recognition (e.g., recognition of fax documents, bank checks, postal addresses). Those applications are particularly well suited for FPGA implementation since a simple processing element (PE) may perform their most basic operations. Consequently, many instances of this PE may be fitted on one FPGA. We present in section 4 two algorithms that fall into this category. We compare the performance of the VIP board with those achieved by dedicated hardware and general processors. 2: ArchitectureOne of the most efficient and cost-effective architecture for parallel vector and matrix processing is the 2D systolic architecture [4, 9, 7, 81. However, this architecture is somewhat restrictive for more general applications. We have thus preferred an SIMD (SingleInstruction Multiple-Data) architecture together with a ...

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