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Abstract:The realization of 30 µm-deep trench isolation in a linear array of butt-coupled 3D CMOS silicon photodetectors is investigated by implementing the formation of a shallow n + -p junction and SiO2-liner over the trench sidewalls as well as the SU-8 filling trenches for passivation. The dependency of the dark I-V curve on the trench isolation scheme is analyzed by monitoring the dynamic dark I-V measurements of four samples including the schemes of single-trench isolation with different widths and the scheme of double-trench isolation. The highest and the lowest dark currents are measured in the detectors with the widest single-trench isolation and the double-trench isolation, respectively.

The Reactive Gas / Wet Cleaning uses reactive gases together with deionized water instead of wet chemistry to produce the corresponding cleaning chemicals for RCA cleaning processes directly on the surface of silicon wafers in the cleaning tool. The fast and strong reactions of the hydrophilic reactants with water and the diffusion through the thin liquid layer covering the wafer surfaces on top and bottom of the wafer lead to process times of 10 seconds, comparable to the wetting of wafer surfaces with diluted liquid chemicals in standard cleaning processes. To reveal the potential of this cleaning approach intentionally with cations contaminated wafers were subjected to the cleaning with NH3(gas)/O3(gas)/H2O (SC1) and HCl(gas)/O3(gas)/H2O (SC2). Vapor phase decomposition atomic absorption spectroscopy showed that the surface contami¬nation of all used elements on the wafer surfaces could be reduced below the detection limits of about 1E+10to 1E+9 cm-2.