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Over the past decade the use of adhesives for electronic interconnect has been driven by the explosive growth of flat panel liquid crystal displays (LCD). Developed and used primarily by Japanese manufacturers of consumer products, particle-loaded adhesive films fulfilled a need in LCDs that could not be met by solder reflow: low temperature, high line density (to 50pm pitch) electrical interconnect to indium tin oxide (ITO) traces on glass.Adhesives may also be used for flip-chip assembly. The advantages of flipchip attach technology are the same for solder or adhesive technology: footprint reduction, low interconnect resistance, short signal line length, and elimination of single-chip packaging costs. Lower parasitics decrease rise times and decrease power requirements. To prevent differential thermal expansion induced solder fatigue, flip-chip attachment using solder reflow requires the use of an underfill adhesive applied in a separate time-consuming process. Adhesive films described in this paper inherently provide an underfill, serve as environmental protection for the chip face, as well as make a solderless electrical connection. Performance results for fine pitch chips have shown stable interconnect resistance below 10 m a for bumped chip applications and approximately 100 mR with unbumped chip test vehicles.The adhesive flip-chip bonding process and environmental stress results will be presented in this paper.

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Chip seals are constructed throughout South Africa as the final layer on top of new or existing pavements. The seal layer provides a waterproof cover for the underlying pavement and a safe, all-weather, dust free riding surface for traffic with adequate skid resistance. The seal layer protects the underlying layer from the abrasive and destructive forces of traffic and the environment. The level of service provided by the seal is governed by its relations to various surface distress types. Distress affects the seal's ability to fulfil its functional and structural requirements. Surface ravelling and fatigue cracking are two major distress types which annul chip seal functionality. Bitumen adhesion and cohesion laboratory tests were therefore conducted and subsequent transfer functions were developed which were utilized in the response quantification of a chip seal finite element model. The response outputs of the finite element models were quantified in terms of wheel load repetitions to the initiation of failure for each distress type. A typical South African seal design assumption suggests a 40:1 equivalent damage ratio for light vehicles versus heavy vehicles. Quantification of the model responses indicated a 3:1 wheel load damage ratio for ravelling and a 2:1 ratio for fatigue cracking. The response model can therefore be utilized as a tool in facilitating the seal design process.