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Abstract. Classically gated infrared (IR) detectors have been implemented using charge-coupled devices (CCD). Bipolar complementary metal-oxide semiconductor (BiCMOS) technology emerged as a viable alternative platform for development. BiCMOS technology has a number of advantages over CCD and conventional CMOS technology, of which increased switching speed is one. The pixel topology used in this work is a reversed-biased diode connected heterojunction bipolar transistor. The disadvantage of CMOS detectors is the increased readout noise due to the increased on-chip switching compared to CCD, which degrades dynamic range (DR) and sensitivity. This yields increased switching speeds compared to conventional bipolar junction transistors. Sensitivity improved from 50 mA∕W (peak) at 430 nm in CCD detectors to 180 mA∕W (peak) (or 180; 000 V∕W) at 665 nm in BiCMOS detectors. Other CMOS IR detectors previously published in the literature showed sensitivity values from 2750 to 5000 V∕W or 100 mA∕W. The DR also improved from 47 and 53 dB to 70 dB. The sensitivity of conventional CCD detectors previously published is around 53 mA∕W. The second advantage is that detection in the near-IR band with conventional silicon integrated technology is possible. This work has shown increased detection capabilities up to 1.1 μm compared to Si detectors.

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The characterization of SiGe diode-connected heterojunction bipolar transistors (HBTs) through measurements of two-circuit configurations is presented. Characterization is done to understand the behavior of these diodes for near-infrared detecting applications at room temperature and 77 K. The two configurations that are considered differ; the first is a base-emitter shorted HBT and the second is a base-collector shorted HBT. The parameters measured are current density-voltage, capacitance-voltage, and noise. The two configurations are implemented using the austriamicrosystems AG 0.35-μm process. The base-emitter shorted configuration exhibits a flatter J C versus V curve when in reverse bias compared with the base-collector configuration. The C − V curves are the same for both configurations. The noise voltage of the base-emitter configuration is 36 and 14.48 μV∕ ffiffiffiffiffiffi Hz p at 102.5 Hz for 293 and 77 K temperature points, respectively, to 14.48 and 12.42 μV∕ ffiffiffiffiffiffi Hz p at 50 kHz for 293 and 77 K, respectively. The noise voltage for the base-collector configuration is 12.6 and 7.56 μV∕ ffiffiffiffiffiffi Hz p at 102.5 Hz for 293 and 77 K, respectively, to 2.228 and 5.981 μV∕ ffiffiffiffiffiffi Hz pat 50 kHz for 293 and 77 K, respectively. This work is done using a standard Si-based technology, where a detector array with readout circuitry can be prototyped as a single chip. The floating base transistor topology is analyzed and used as a foundation for this work. The characteristics of a floating base configuration result in a wide depletion region, large-series resistance, and small-series capacitance. When shorting the base with the emitter and collector, respectively, compared with a floating base configuration, a smaller depletion region, reduced series resistance, and larger series capacitance are observed.