Virtual FPGA (V-FPGA) architectures are useful as both early prototyping testbeds for custom FPGA architectures, as well as to enable advanced features which may not be available on a given host FPGA. V-FPGAs use standard FPGA synthesis and placement tools, and as a result the maximum application frequency is largely determined by the synthesis of the V-FPGA onto the host FPGA. Minimal net delays in the virtual layer are crucial for applications, but due to increased routing congestion, these delays are often significantly worse for larger than for smaller designs. To counter this effect, we investigate three different placement strategies with varying amounts of manual intervention. Taking the regularity of the V-FPGA architecture into account, a regular placement of tiles can lead to an 37 % improvement in the achievable clock frequency. In addition, uniformity of the measured net delays is increased by 39 %, which makes implementation of user applications more reproducible. As a trade-off, these manual placement strategies increase area usage of the virtual layer up to 16 %.

Recently proposed quantum systems use frequency multiplexed qubit technology for readout electronics rather than analog circuitry, to increase cost effectiveness of the system. In order to restore individual channels for further processing, these systems require a demultiplexing or channelization approach which can process high data rates with low latency and uses few hardware resources. In this paper, a low latency, adaptable, FPGA-based channelizer using the Polyphase Filter Bank (PFB) signal processing algorithm is presented. As only a single prototype lowpass filter needs to be designed to process all channels, PFBs can be easily adapted to different requirements and further allow for simplified filter design. Due to reutilization of the same filter for each channel they also reduce hardware resource utilization when compared to the traditional Digital Down Conversion approach. The realized system architecture is extensively generic, allowing the user to select from different numbers of channels, sample bit widths and throughput specifications. For a test setup using a 28 coefficient transpose filter and 4 output channels, the proposed architecture yields a throughput of 12.8 Gb/s with a latency of 7 clock cycles.

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Recent publications show a rise of ambipolar transistor technology research and associated implementations of multi-function logic cells in these technologies. Special properties of these technologies enable implementations of Universal Logic Modules (ULMs) using few transistors, which draws renewed interest to use such ULMs as basic logic blocks for FPGA architectures. Unlike N -input Lookup Tables (LUTs), most ULMs only implement a fixed subset of the possible Boolean functions.In this work, we first adapt the Verilog-to-Routing (VTR) 8.0 toolflow to target such reduced-function ULM primitives. We then modify VTR's flagship 40nm architecture to use an ULM primitive instead of LUTs, modeling the double-gate carbon nanotube FET 8-function logic gate CNT-DR8F published by Liu et al. Using VTR's extensive benchmark framework, we analyze effects caused by the limited set of function offered by these primitives. To counter some of the observed effects, we present various clustered architectures, where multiple ULM cells are combined in a logic block. We conclude with an analysis of various parameters which affect performance of the different implementations.