Slip is a primary concern in Rapid Thermal Processing (RTP). Diagnostics for slip are compared, including: visual inspection, differential interference contrast microscopy (Nomarski), X-ray topography, decorative etching and optical surface scanning. Data from each technique are presented. RTP control parameters (temperature uniformity, heat up and cool down rates, edge cooling) and substrate parameters (wafer size, oxygen content, edge damage) which may have an effect on slip are discussed. Typical results for implant annealing sequences on a water-wall DC arc lamp RTP system are presented and used to suggest techniques for process optimization.

Detecting impurities or contaminations in the ultra thin silicon oxide layer is one of the most serious challenges in wafer processing as device is scaled down toward deep sub-micron. These impurities or contaminations will create charge traps in the oxide layer and degrade gate oxide integrity (GOI). The MOS Capacitance-Voltage method which has been used to study the electrical charges in relative thicker oxide layer (> 5 nm) cannot detect, however, these contaminations related charges in the ultra thin silicon oxide layer. In this article, a new method has been developed to determine the electrical charges associated with the contaminations in an ultra thin oxide layer using Hg-Schottky capacitance-voltage method. The oxide layers of 1.2 nm in thickness with and without Cu-contamination have been tested with this new method. The results show that the new method can be used to qualitatively identify the electrical charges trapped in the ultra thin silicon oxide layer and the trapping levels associated with the contamination. The interactions among sub-stochiometric oxide structure and electron traps introduced by the metal impurities have been discussed.