Phase change materials (PCMs) are characterized by their fast transformation speeds from their amorphous to crystalline states, with each state having distinct properties. These unique and distinct properties can be used for data storage and even computation, with their proposed application to enable neuromorphic computing. Ge2Sb2Te5 (GST) is a widely used PCM due to its fast-switching speeds and good data storage capabilities. However, it also has a low crystallization temperature, which makes long-term data storage (>10 years) difficult. One way to improve this is to alloy the material with carbon, which has been found to increase both the transformation temperature and the stability of the cubic phase.To understand the effects of carbon, we are investigating how atomic structure transformations are modified by carbon doping (from 0% to 12%, molar) via in situ X-ray scattering, including X-ray diffraction (XRD) and pair distribution function (PDF) analysis. These methods provide access across local, mid-range, and average structure scales, and variations thereof through their amorphous-to-crystalline transformation. By identifying this atomic structure over the process, we can establish structure-property relationships and how these vary with composition. This new understanding is necessary to tailor GST, or other PCMs, for current and future applications, such as data storage and computing.

The yield of chip packaging operations is a function of the surface finish that is solderable and wire-bondable. It has been shown that the use of palladium (Pd) plated lead-frame for packaging has improved the processing cost and reliability by simplifying the process integration [1]. Pd can also be used as a sacrificial layer to protect the copper (Cu) substrate material from oxidation and interdiffusion before the SnPb solder application. In packaging applications, Pd is advantageous in forming a Ni(Pd)Si allowing a lower sheet resistance at higher temperatures as compared to the NiSi in addition to much better surface morphology [2]. The new integration schemes of Pd into the circuitry at the packaging level also require a CMP application where the Pd is deposited on the dielectric layer with bond-pad recess and polished to form a Pd based pad surrounded by Ni [3]. In combination with the applications of the 2.5 and 3-D microelectronics packaging technologies, the CMP electivity becomes critical where a competitive removal rate is desired between the Cu, Cu-barrier (TaN) and Ni films It has been demonstrated on W-CMP in an earlier study that the 1:1:1 removal rate selectivity of the W/Ti/TiN layers can be achieved through adjusting CMP formulations in terms of the slurry chemistry and the particle concentrations. The systematic study has demonstrated a methodology for developing optimal CMP configurations for the newly introduced films to CMP applications based on electrochemical evaluations [5]. In this paper, we study the removal rate selectivity for Pd integrated packaging level CMP applications through electrochemical and surface energy evaluations in commercial bulk and barrier CMP slurries. It can be seen that the thin film dissolution rates relate to the surface passivation as well as the surface energy measured by the contact angle evaluations on the Cu, Pd, TaN and Ni wafer coupons. Pd being a novel metal shows strong passivation that results in minimal dissolution in the slurry environment which requires alternative formulations for CMP slurries to promote the removal rate performance. References: Kajija, I.V., Absy, J.A., Maisano, J.J., Kudrak, A.J., Shimada, S. “Thin Multilayer Palladium Coating for Semiconductor Packaging Applications. Part I: Solderability. NASF Surfcae Technology White Papers, 80 (6), 6-19 (2016). Karabko, A., Dragasius, E. Nisi and Ni(Pd)Si as possible interconnect and electrode material for film bulk acoustic resonators and microelectromechanical systems. Journal of Vibroengineering, 15 (1), 2013. Eisa, M., Zinn, B. “Aluminum Enhanced Palladium CMP Process” US Patent 8,288,283, October 16, 2012. Song, C., Wang, Z., Chen, Q., Cai, J., Liu, L. “High aspect ratio copper through-silicon-vias for 3D integration”, Microelectronic Engineering, 85 (10), P1952-P1956, Yagan, R., Basim, G.B., “A Fundamental Approach to Electrochemical Analyses on Chemically Modified Thin Films for Barrier CMP Optimization," ECS J. Solid State Sci. Technol. 8-5, P3118-P3127, 2019.

Palladium (Pd) is a chemically inert material known for its ability to improve processing cost and reliability for the packaging level microelectronics integration. In addition, it is used as a sacrificial layer for copper (Cu) integration as a barrier material to protect the copper from oxidation. Successful implementation of Pd requires chemical mechanical planarization (CMP) process in both applications, where selectivity is desired between the Cu, tantalum nitride (TaN), and nitride (Ni) films against Pd. This paper focuses on removal rate selectivity tuning for Pd thin films in a commercial silica-based Cu-CMP slurry compared to a baseline silica slurry as a function of the slurry temperature. Detailed analyses of the integrated materials are presented, investigating the effect of temperature on surface wettability and CMP selectivity. Pd passivation is also presented by electrochemical analysis in the presence of an oxidizer for the selected polishing slurries. It is observed that lowering the slurry temperature promotes palladium CMP removal rate selectivity against Ni, Cu, and TaN by modifying slurry viscosity and wafer surface wettability with no detrimental effect observed on the surface defectivity.