O n e supercomputer characteristic that has remained constant with time is the packaging challenge. In the 1960s, the Control Data 6600 used threedimensional (3Dl discrete mnsistor and resistor logic modhes' with wiring tuned by lengths and Freon cooling, which permitted a reduction in the physical size of the computer and a significant performance improvement. Its successor, the CDC7600, continued that evolution with even greater packing density by using extremely small transistors and resistors packaged in larger 3D logic modules. Cray Research used early integrated circuits in much smaller packages and produced the Cray l a with impressive performance and small size.Those early, complex high-performance computers shared the characteristic of innovative packaging and cooling, allowing them to operate at millions of floatingpoint operations (flops) per second. Although these systems realized some performance gain from reduced interconnect distance, ';host of the speed improvements came from ever faster logic and memory. However, as the rate of increase in logic speed gradually slowed, computer architects were forced to reduce the interconnect distances to gain further performance.In seeking more performance, the computer architect looks at several factors: (i) faster logic gates, (ii) greater logic density as measured by gates per chip, and (iii) denser packaging to reduce the interconnect delays. This pressing need started the trend that will lead to a few large-scale integration (LSI) custom "bare dies" (that is, unpackaged circuits) per processor accompanied by baredie memory. Logic and memory will be included in a multichip module (MCM) to achieve a compact highperformance superprccesor. Multiple MCMs can be packaged into a physically small parallel system that has impressive performance and is scalable to the needs of the marketplace. Clearly, this level of integration will be a serious contender in the supercomputer design race. However, this compact 3D package has significant challenges remaining to be solved. Problems-such as L. M. Thorndyke is at DataMax, Edina, MN 55435. J. P. power distribution, ground bus noise, removal of heat, interconnect reliability and impedance control, and ready parts replacement without service interruption-place new demands on the packaging engineer.Today we are seeing the emergence of the Massively Parallel Systems (MPSs) that use standard packaged logic and memory chips. The typical MPS, with a few thousand standard microprocessor chips and tens of thouing will result in bare microprocessors and memory die, drastically reducing the processor-to-memory distance and increasing system performance. This packaging will gradually evolve into a 3D structure that closelv resembles some current sumrcomputers. When this occurs, the costs of a massively parallel engineering and manufacturing development will approach that of supercomputers-they both will be expensive. However, the production costs for the MCM-based systems will be lower because of the automated MCM assembly tooling a...
