Heat dissipation in 3D chip stacks suffers from multiple thermal interfaces. The effective thermal resistance of the bond-line between individual dies, with the electrical interconnects can be minimized by the introduction of thermal conductive underfills. Up to now, only sequentially formed underfills result in true percolation and hence, thermal conductivities of more than 1 W/m-K. In this study, we report on various aspects to consider during the formation of percolating thermal underfills, by centrifugal filling of micron-sized particles and the subsequent backfilling of an epoxy by capillary action. Particle assemblies within silicon-glass cavities were investigated for mono and poly-dispersed spherical and facetted particles with characteristic dimension in the range of 15 μm to 50 μm. Clogging of particles between silicon pillars could be mitigated at low particle fluxes dispensed by the hour glass principle. Particle shadowing behind the silicon pillars could be eliminated by ultrasonic agitation. Finally, close to crystalline phases could be identified for the mono-dispersed particles, compared to a random packing for the poly-dispersed particles. The effective pore diameter of the particle beds was experimentally derived from a backfilling experiment with viscosity standards. A normalized pore diameter of 0.15, 0.17 to 0.20 and 0.11 was observed for mono and poly-dispersed spherical and facetted particles, respectively. The backfill dynamics can be predicted with those values and the Washburn equation. Cavities filled with particles down to 30 μm diameter could be filled completely with the available low viscosity epoxy system. Finally, we report on the re-arrangement of filler particles due to capillary action and viscous drag, during the backfilling process. Defects are minimal for fluids of low surface tension and high viscosity. Hence, only 1 area-% of defects were observed from the infiltration of epoxies

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The current feed capacity of electrical interconnects is mainly limited by the poor electromigration (EM) resistance of lead free-solder interconnects. Thus, the community investigates alternative interconnect approaches and materials, e.g. all-copper interconnects using copper pastes. EM is an electron scattering based transport of metal atoms, occurring at high current densities, resulting in voids and thus finally leads to an open interconnect. For all-copper interconnects, it is expected that the maximum current density could be increased, while power losses can be mitigated, due to the higher EM resistance and reduced resistivity of copper compared to solder, respectively. However, all-copper interconnects formed by copper pastes applied without pressure result in a porous copper interconnect morphology with unknown EM performance. Thus, the authors report on results of EM tests on nanoporous copper films. The investigated copper paste is especially designed to be used for flip chip interconnects and contains nano and micron sized copper particles. Paste films were performed by doctor blading, followed by a sintering process at 200°C in formic acid. SEM analysis on FIB cross-sections of sintered films revealed the fusion of the nanoparticles to a nanoporous, sponge like morphology with embedded microparticles. Furthermore, a porosity of approximately 30% could be identified. The high porosity results in a non deterministic electrical network with a measured effective resistivity of ~10 μΩ cm, which is five times higher than the one of bulk copper (1.78 μΩ cm). For detailed investigations of the EM characteristics a setup, as well as a specific test sample layout were designed and implemented. The setup is capable to feed a current of up to 40 A to eight serial samples in a temperature range from room temperature to 250°C in ambient atmosphere. The test samples consist of copper lines, relief printed onto a silicon based carrier substrate, to bridge a 200 μm wide gap between two electrochemically deposited copper electrodes. The voltage drop across the copper line can be measured while driving the current through the line, by four point probing. In addition, a platinum based thermocouple (PT1000) is implemented on the carrier substrate beneath the nanoporous copper. It allows to prove the temperature of the nanoporous copper, to derive exact test conditions and the temperature coefficient of resistance of the nanoporous copper. Initial tests of samples exposed to elevated temperatures above 90°C, but without any current applied, resulted in the resistance increase of the nanoporous copper due to oxidation. Accordingly, a photoresist coverage was applied on the copper lines to mitigate the copper oxidation to levels acceptable for EM testing. A series of EM tests were then performed under constant current conditions to derive the EM kinetics and to explore the damage mechanisms. At current densities of 1 MA/cm^2 and a sample temperature of 90°C, the observed ‘time to failure’ of the nanoporous copper was more than six times higher than the one of tin based lead free solder. Furthermore, the authors will summarize their findings of the EM study performed on the nanoporous copper.