Abstract-Interference alignment (IA) is a cooperative transmission technique for the interference channel.This paper describes two testbeds that implement real-time Multiple-input multiple-output (MIMO) IA for a network with three 2-antenna user pairs using software defined radio techniques: a PCbased testbed for rapid prototyping of potential IA protocols and an embedded testbed for evaluating IA under real-world computational constraints. The IA implementations rely on a wired backbone to share global channel state information (CSI) and a shared clock for frequency and timing synchronization. The testbeds are used to demonstrate the viability of IA, and to compare its robustness with several alternative transmission strategies, such as 2 × 2 MIMO TDMA, in terms of sum-rates. Results show that we are able to successfully achieve over-the-air IA in our three-user 2 × 2 MIMO testbed. The paper highlights key challenges with the practical realization of IA that are encountered while developing the testbed and identifies areas for future research.

Interference alignment is a technique for designing transmit precoders that is known to achieve the maximum multiplexing gain in the interference channel. Prior work on interference alignment has assumed sum-power constraints in designing the transmit precoders. In practice, however, each transmit antenna has its own power amplifier which constrains the power radiated from each antenna. This paper proposes and analyzes two algorithms for performing interference alignment with per-antenna equality and inequality power constraints. It is proven that incorporating inequality constraints can be done arbitrarily and does not affect the feasibility of interference alignment. Further, we show that incorporating equality constraints is more difficult and requires more antennas for interference alignment to be feasible, especially in the case of single-stream systems. It is shown through analysis and numerical sum-rate calculations that per-antenna inequality constraints result in a systematic power loss versus the cases of per-antenna equality constraints or no constraints at all.

Globally synchronous, multi-drop, bidirectional microprocessor system interfaces have the advantages of low latency and no synchronization penalty, and typically run at 100-120MHz. Maximum operating frequency is limited by the time required for a signal transition initiated at the driving end to settle and reliably get sampled at the receiving end. Typical source-terminated systems (such as HSTL [1]) require a round-trip transmission-line propagation delay to terminate the signal. With parallel terminated systems such as GTL[2] with 2 nodes, a bus turnaround low-to-low switch with no dead-cycle needs a round-trip propagation delay to settle and be sampled reliably. The dynamic termination logic (DTL) system reduces the settling time to a one-way delay, by having the driver at the receiving end terminate the signal, and raises the signaling frequency to 150-200MHz.A major concern with on-chip termination is to maintain nearly constant termination resistance over process, supply voltage, temperature (PVT), and output signal voltage variations. The impedance control and linearization schemes presented here address this concern. In addition, these circuits limit rail bounce, and maintain nearly constant driver resistance during switching. The circuits are implemented on the next generation SPARC microprocessor [3].Figure 15.1.1 shows a general 2-node DTL signaling system and its signal waveforms. The driver at the receiving end acts as a termination resistor to positive IO supply voltage (vddo). The output resistance of the pullup and pulldown units are matched to the characteristic impedance (Zo) of the transmission line. The system requires just a one-way propagation delay for the line to settle, even when a bus turnaround low-to-low switch occurs without an intervening dead-cycle. The signal voltage swing is vddo/2 to vddo; the driver is push-pull. The receiver is differential comparing the input signal to a reference voltage (vref=0.75*vddo).For 3-node systems, two methods may be used (Figure 15.1.2). If the length of the middle stub is <1 inch, scheme-1 gives better performance. Otherwise, scheme-2 must be used to prevent oxide overvoltage. This is because scheme-1 has larger voltage overshoots than scheme-2 when a middle driver switches from drive-low to receive (tristate), large enough to exceed process specification for gate-oxide overvoltage (2.1V DC, 2.4V AC). For systems with more than 3 nodes, scheme-1 is used since scheme-2 would require low pulldown resistance (resulting in larger currents and device area).The DTL output driver is linearized, impedance-controlled, and slew-rate controlled, and functions as both a driver and a pullup terminator. Each pullup and pulldown output unit consists of multiple elements of varying widths one of which is permanently enabled, while the others are enabled or disabled according to an impedance-control code to give a desired net DC output impedance across PVT variations. This code follows a "thermometer-code"only one bit changes per code update, and the order of bit c...