and 5 highlight how relaxed gate pitch improves fT which results from not only lower capacitance from wider gate-toWe report record RF performance in 45-nm silicon-oncontact spacing but also enhanced stress response (higher insulator (SOI) CMOS technology. RF performance scaling transconductance gm) of the device. Fig. 6 shows peak fTvs. with channel length and layout optimization is demonstrated. I/Lpoly for SOI CMOS from 90 to 45-nm nodes, Peak fT's of 485 GHz and 345 GHz are measured in floatingdemonstrating that RF performance scaling continues with body NFET and PFET with nearby wiring parasitics (i.e., gateLpoly in deep sub-lOOnm CMOS technologies. Figs. 7 and 8 to-contact capacitance) included after de-embedding, thus show the gm and Cgate (= Cgs + Cgd) vs. I/Lpoly extracted at representing FET performance in a real design. The measured peak fT condition for 45-nm SOI NFETs and PFETs, fT's are the highest ever reported in a CMOS technology. Bodyindicating the well controlled channel with Lpoly. contacted FETs are also analyzed that have layout optimized Source/drain contact pitch as well as gate poly pitch can be for high-frequency analog applications. Employing a notched optimized for RF applications, and Figs. 9 and 10 show the body contact layout, we reduce parasitic capacitance and gate measuredfT and gm for minimum poly pitch SOI NFETs and leakage current significantly, thus improving RF performance PFETs with an Lp of 31 nm as a function of gate bias, with low power. For longer than minimum channel length and a where wider source/drain contact pitches result in higherfT, body-contacted NFET with notched layout, we measure a peak due to the lowering of gate-to-contact capacitance with fT of 245 GHz with no degradation in critical analog figures of fewer contacts. Note also in Figs. 9 and 10 that the gm of the merit, such as self-gain. device is not affected much by the potential increase of source/drain resistance with fewer contacts. Introduction B. Body-contacted SQL FET analog/RF Performance This high-performance 45-nm SOI technology features 1.16 nm gate oxide, dual stress liners (DSL), eSiGe PFET, advancedIn high-frequency analog circuits, device self-gain (gm activation annealing, and stress memorization techniques over output conductance gds) and matching between (SMT) [1]. Advanced immersion lithography employed neighboring devices are important. For such consideration, provides good channel length control and supports multiple we investigate SOI NFETs with longer than minimum gate pitches. To investigate the suitability of this high channel length (for high self-gain) and a body contact (for performance CMOS technology for millimeter-wave digital good matching due to reduced VBS fluctuation). Fig. 11 and analog system-on-chip (SoC) applications [2, 3, 4], Sshows the measured self-gain as a function of gate bias for a parameter measurements at frequencies up to 110 GHz were floating-body NFET with 32 nm Lp01y and body-contacted performed to analyze RF/analog characteristics of partially-NFET w...

Abstract-This paper presents a modeling strategy of human driving behavior based on the controller switching model focusing on the driver's collision avoidance maneuver. The driving data are collected by using the three-dimensional driving simulator based on CAVE, which provides stereoscopic immersive virtual environment. In our modeling, the control scenario of the human driver, that is, the mapping from the driver's sensory information to the operation of the driver such as acceleration, braking and steering, is expressed by Piecewise Polynomial (PWP) model. Since the PWP model includes both continuous behaviors given by polynomials and discrete logical conditions, it can be regarded as a class of Hybrid Dynamical System (HDS). The identification problem for the PWP model is formulated as the Mixed Integer Linear Programming (MILP) by transforming the switching conditions into binary variables. From the obtained results, it is found that the driver appropriately switches the 'control law' according to the sensory information. Also, the driving characteristics of the beginner driver and the expert driver are compared and discussed. These results enable us to capture not only the physical meaning of the driving skill, but also the decision-making aspect (switching conditions) in the driver's collision avoidance maneuver.

This paper considers the design problems of a delay-dependent robust and non-fragile guaranteed cost controller for singular systems with parameter uncertainties and time-varying delays in state and control input. The designed controller, under the possibility of feedback gain variations, can guarantee that a closed-loop system is regular, impulse-free, stable, an upper bound of guaranteed cost function, and non-fragility in spite of parameter uncertainties, time-varying delays, and controller fragility. The existence condition of the controller, the controller's design method, the upper bound of guaranteed cost function, and the measure of non-fragility in the controller are proposed using the linear matrix inequality (LMI) technique. Finally, numerical examples are given to illustrate the effectiveness and less conservatism of the proposed design method.

As an essential clock-system component, millimeter-wave dividers have been implemented for V-and W-band channels [1][2][3][4][5][6][7][8]. This has also served as a standard benchmark vehicle that reveals highspeed and low-power performances of a technology. Through technology scaling, CMOS CML static divider high-frequency performances have been scaled [6][7][8], and they are comparable to dividers in other technologies [1][2][3][4][5]. In addition to the device performance, circuit design and measurement determine the divider high-speed and wide frequency range performance. One of the uncertainties in CML static divider measurement is pulling and locking hysteresis. By using CML static divider topology, the divider has been assumed to have a fixed wide operation range, from DC to the f div,max , the maximum input-referred divider operational frequency. In fact, the CML static dividers show a certain degree of locking hysteresis, similar to injection-locking dividers [9]. When the circuit sensitivity curve is measured, it is not clear where to set the threshold. Depending on the method, a sensitivity curve can be optimistic or pessimistic. A similar problem lies in the f div,max , since it changes depending on the status of a divider. Also, there have not been any analytic results that can interpret the circuit parameters and performance, in spite of the common use of sensitivity curve in literatures.The CML static divider schematic is shown in Fig. 25.5.1. It has CML-based master-slave FF latches, with AC-coupled RF input and separate DC bias input. To maximize the divider performance, a cellbased FET layout is used with pitch relaxation. It effectively improves the device g m by enhancing the stress liner efficiency through the opening. The FET parasitic capacitance is reduced due to the increased gate-to-contact spacing. By its nature, the divider exhibits highly nonlinear behavior. It has multiplication as a singlebalanced mixer, and the circuit behaviors are quite different in selfoscillation and input-locked modes. An approximate and linearized circuit analysis is used to obtain sensitivity curve and locking hysteresis models. The approximation begins from the tail current i T modulation by input v I , and the resulting differential-pair g M,D changes. By assuming that the input is much smaller than the bias tail current I T , the modulated differential pair g M,D is derived with power series expansion and high-order term omission. The mixing is approximated by ignoring high-frequency terms with an assumption that they are low-pass filtered by the circuit [8]. The result will be more relevant to the high-frequency part of the divider operation due to the assumption. Another assumption is that the circuit is bistable between self-oscillation and input-locked modes. A steadystate circuit equation is established by assuming 270˚ phase between differential-pair input and output node v O . In the absence of input signal v I , the self-oscillation condition and frequency are obtained. The loading capacitance is ...

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