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The electrical characteristics of a low-temperature polycrystalline silicon thin-film transistor (TFT) with a source-contacted light shield (SCLS) are observed and analyzed. Compared with that of a conventional TFT without a light shield (LS), the on-current of the TFT with an SCLS is lower because the SCLS blocks the fringing electric field from the drain to the active layer. Furthermore, the gate-to-source capacitance (C gs ) of the TFT with an SCLS in the off and saturation regions is higher than that of a conventional TFT, which is due to the gate-to-LS capacitance (C g-LS ). The electrical characteristics of the TFT with an SCLS are thoroughly investigated by two-dimensional device simulations, and a semi-empirical C g-LS model for SPICE simulation is proposed and verified.

The effect of lightly doped drain (LDD) doping concentration on the capacitance of a lowtemperature polycrystalline silicon (LTPS) thin-film transistor (TFT) is investigated. An anomalous gate-to-source capacitance phenomenon is observed: first, the capacitance decreases, and then it increases according to the gate voltage in the saturation region. This phenomenon is not affected by the subgap density-of-states and arises as the doping concentration of the LDD region is reduced. To investigate the effects of each source and the drain LDD dose on the gateto-source capacitance, two-dimensional device simulations were conducted in which each dose of the source and drain LDD was changed individually. The reduced controllability of the source voltage to the gate charge in the saturation region due to the increased resistance of the source LDD region with low LDD dose is identified as the reason for this anomalous capacitance phenomenon.