CMOS RF has evolved from a novelty to a necessity with the mergence of all analog and digital functionality into a single chip for standards such as Bluetooth and WLAN/802.11. The stringent performance requirements associated with cellular standards such as GSM, however, has either limited the level of RF transceiver integration, or compelled the use of alternative technologies such as BiCMOS or bipolar [1]. In this paper, a fully integrated quad-band GSM/GPRS transceiver, fabricated in a 0.18µm CMOS process, is described. This device integrates all the RF and analog transceiver functionality in a single-silicon substrate while meeting the performance requirements of the GSM standard. The challenges of CMOS technology are overcome by careful architectural decisions, appropriate circuit-design techniques, and self-calibrated analog circuits. Wherever possible, the availability of high-density CMOS logic is exploited by pushing the design complexity into the digital domain. Figure 17.6.1 shows the block diagram of the transceiver IC and the necessary external RF components. Only a switchplexer, a power amplifier module, input SAW filters, and matching components are needed to complete the RF front-end. All the VCOs, TX and RX signal path filters, and PLLs are integrated.The receiver uses a low-IF architecture. Compared to zero IF, this architecture is more tolerant to impairments due to 1/f noise, DC offsets, and finite receiver IIP2. The LNAs are implemented as fully differential common-source amplifiers with on-chip inductive degeneration for impedance matching and gain peaking. The LNAs also implement a low-gain mode. Following the LNAs, quadrature mixers down-convert the desired RF signal to a low IF. The low-IF section of the receiver consists of a 5 th -order complex Butterworth filter and PGA. This is formed by cascading five complex pole stages, each implemented as shown in Fig. 17.6.2 [2]. Using a 26MHz crystal as a reference, an on-chip tuning circuit estimates the RC time constant on the transceiver. The capacitor array C 2 is then programmed to correct for process-and temperature-related variations in the filter frequency response. Each complex filter stage contributes to the rejection of the GSM blockers and the image signal, and provides programmable amplification of the desired signal. The gain distribution and the sequencing of the filter poles are selected to maximize the overall RX SNR. This programmable-gain IF filter, combined with the LNA gain step, incorporates 100dB of gain programmability. A DC-offset calibration (DCOC) circuit is used to prevent the IF gain stages from saturating. Resistive cross-coupling between the I and Q channels of the filter cause the DC offsets on the I channel to influence the Q channel and vice versa. In order to keep the DCOC loops independent from each other, the DC offset is measured and corrected as shown in Fig. 17.6.2. Following the complex filter, a low-IF demodulation circuit down-converts the IF I and Q signals to baseband frequencies using a digitally syn...
