A method of graphene transfer without metal etching is developed to minimize the contamination of graphene in the transfer process and to endow the transfer process with a greater degree of freedom. The method involves direct delamination of single-layer graphene from a growth substrate, resulting in transferred graphene with nearly zero Dirac voltage due to the absence of residues that would originate from metal etching. Several demonstrations are also presented to show the high degree of freedom and the resulting versatility of this transfer method.

A decade after the discovery of graphene flakes, exfoliated from graphite, we have now secured large scale and high quality graphene film growth technology via a chemical vapor deposition (CVD) method. With the establishment of mass production of graphene using CVD, practical applications of graphene to electronic devices have gained an enormous amount of attention. However, several issues arise from the interfaces of graphene systems, such as damage/unintentional doping of graphene by the transfer process, the substrate effects on graphene, and poor dielectric formation on graphene due to its inert features, which result in degradation of both electrical performance and reliability in actual devices. The present paper provides a comprehensive review of the recent approaches to resolve these issues by interface engineering of graphene for high performance electronic devices. We deal with each interface that is encountered during the fabrication steps of graphene devices, from the graphene/metal growth substrate to graphene/high-k dielectrics, including the intermediate graphene/target substrate.

Direct graphene transfer is an attractive candidate to prevent graphene damage, which is a critical problem of the conventional wet transfer method. Direct graphene transfer can fabricate the transferred graphene film with fewer defects by using a polymeric carrier. Here a unique direct transfer method is proposed using a 300 nm thick copper carrier as a suspended film and a transfer printing process by using the polydimethylsiloxane (PDMS) stamp under controlled peeling rate and modulus. Single and multilayer graphene are transferred to flat and curved PDMS target substrate directly. With the transfer printing process, the transfer yield of a trilayer graphene with 1000 µm s −1 peeling rate is 68.6% of that with 1 µm s −1 peeling rate. It is revealed that the graphene transfer yield is highly related to the storage modulus of the PDMS stamp: graphene transfer yield decreases when the storage modulus of the PDMS stamp is lower than a specific threshold value. The relationship between the graphene transfer yield and the interfacial shear strain of the PDMS stamp is studied by finite-element method simulation and digital image correlation.

In this paper, we report the alleviation of the Fermi-level pinning on metal/n-germanium (Ge) contact by the insertion of multiple layers of single-layer graphene (SLG) at the metal/n-Ge interface. A decrease in the Schottky barrier height with an increase in the number of inserted SLG layers was observed, which supports the contention that Fermi-level pinning at metal/n-Ge contact originates from the metal-induced gap states at the metal/n-Ge interface. The modulation of Schottky barrier height by varying the number of inserted SLG layers (m) can bring about the use of Ge as the next-generation complementary metal-oxide-semiconductor material. Furthermore, the inserted SLG layers can be used as the tunnel barrier for spin injection into Ge substrate for spin-based transistors.

A high-performance top-gated graphene field-effect transistor (FET) with excellent mechanical flexibility is demonstrated by implementing a surface-energy-engineered copolymer gate dielectric via a solvent-free process called initiated chemical vapor deposition. The ultrathin, flexible copolymer dielectric is synthesized from two monomers composed of 1,3,5-trimethyl-1,3,5-trivinyl cyclotrisiloxane and 1-vinylimidazole (VIDZ). The copolymer dielectric enables the graphene device to exhibit excellent dielectric performance and substantially enhanced mechanical flexibility. The p-doping level of the graphene can be tuned by varying the polar VIDZ fraction in the copolymer dielectric, and the Dirac voltage (V ) of the graphene FET can thus be systematically controlled. In particular, the V approaches neutrality with higher VIDZ concentrations in the copolymer dielectric, which minimizes the carrier scattering and thereby improves the charge transport of the graphene device. As a result, the graphene FET with 20 nm thick copolymer dielectrics exhibits field-effect hole and electron mobility values of over 7200 and 3800 cm V s , respectively, at room temperature. These electrical characteristics remain unchanged even at the 1 mm bending radius, corresponding to a tensile strain of 1.28%. The formed gate stack with the copolymer gate dielectric is further investigated for high-frequency flexible device applications.