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In this article, an linearization technique using a gate voltage adaptation of a common gate stage for a cascode CMOS power amplifier (PA) is presented. The tracking of minimum in‐band third‐order intermodulation distortion by controlling with respect to instantaneous power level enhances the linearity of CMOS PA over a wide range of operation level. The experimental results show that the CMOS PA with proposed scheme has an overall efficiency of 34.6% and a gain of 25.8 dB at an average output power of 27 dBm. Under this condition, the adjacent channel leakage ratio is <–34.8 and 5.4 dBc lower when compared with the use of no linearization technique.

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