Chemotherapy induced peripheral neuropathy (CIPN), a toxic side effect of some cancer treatments, negatively impacts patient outcomes and drastically reduces survivor’s quality of life (QOL). Uncovering the mechanisms driving chemotherapy-induced CIPN is urgently needed to facilitate the development of effective treatments, as currently there are none. Observing that C57BL/6 (B6) and 129SvEv (129) mice are respectively sensitive and resistant to Paclitaxel-induced pain, we investigated the involvement of the gut microbiota in this extreme phenotypic response. Reciprocal gut microbiota transfers between B6 and 129 mice as well as antibiotic depletion causally linked gut microbes to Paclitaxel-induced pain sensitivity and resistance. Microglia proliferated in the spinal cords of Paclitaxel treated mice harboring the pain-sensitive B6 microbiota but not the pain-resistant 129 microbiota, which exhibited a notable absence of infiltrating immune cells. Paclitaxel decreased the abundance of Akkermansia muciniphila, which could compromise barrier integrity resulting in systemic exposure to bacterial metabolites and products – that acting via the gut-immune-brain axis – could result in altered brain function. Other bacterial taxa that consistently associated with both bacteria and pain as well as microglia and pain were identified, lending support to our hypothesis that microglia are causally involved in CIPN, and that gut bacteria are drivers of this phenotype.

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As CMOS technology is scaled beyond 45nm, SOC/SiP design for wireless chips is increasingly constrained by fundamental technology limits, resulting in challenges including parametric variability, leakage, active power, signal integrity, and diminished performance improvement. New materials and innovative device structures are needed to extend CMOS scaling and integrate disruptive "More than Moore" functionality, but these can have adverse impact on manufacturing cost and risk. Hence, tradeoff analysis spanning process, device, circuit, memory, package, architecture, software, and business disciplines is required during the advanced technology development cycle to explore and cooptimize technology and design choices. Such methodology, in conjunction with judicious use of test chips, also provides for a bridge from innovative technology solutions to mainstream product adoption.Several approaches are currently in use for ad-hoc exploration of advanced technology and design -typically based on spreadsheet analysis, guru consultation, and/or full trial designs. With the exploding complexity of the optimization space, subject matter knowledge and expert experience needs to be complemented with a structured methodology and tools. A "Holistic Pathfinding" methodology is proposed for addressing technology and design tradeoffs early in the development cycle to allow co-optimization all the way up to the system architecture level. A virtual design flow that allows rapid estimation of performance, power and cost attributes of a potential product, as a function of a given set of process or design assumptions is described as shown in Figure 1. Key target features of such a virtual flow and a summary of the attributes of several candidate point tools is presented. Requirements for the tools and methodologies to be used for Pathfinding across the span of disciplines are outlined. In order to enable system cost and performance/power analyses, the requirements for predictive models that describe variability, leakage, devices, interconnect, and DFM attributes are identified.Examples of Pathfinding application for co-optimization of memory technology and architecture, reduced parametric variability using restricted physical design rules, and exploration of 3D chip stacking are presented to highlight the requirements