No abstract

This paper focuses on the FPGA implementation of a slew-rate reduction (SR) shaping function for envelope tracking (ET) power amplifiers (PAs). The SR envelope has been proved effective to trade-off power efficiency and linearity in ET PA systems where the envelope tracking modulator (ETM) is bandwidth limited. However, the implementation issues need to be addressed when targeting high clock rates to cope with current 5G new radio wide-band signals. This paper shows the FPGA implementation of the SR envelope generation. We explore the use of high-level synthesis (HLS) for the SR envelope generation to evaluate the performance and resource usage of the hardware architecture. The HLS design is also compared with a handwritten hardware description language (HDL) version. An indepth analysis shows strengths and limitations of the HLS design to meet the timing constraints when considering a throughput of 614.4 MSa/s.