The trend of increasing digital system performance by downscaling the device size poses daunting challenges in system design due to the increased power density, higher I/O count, interconnect bandwidth, and timing closure requirements. Silicon carrier with Through Silicon Vias (TSVs) or TSI technology is identified as a system and packaging level solution to overcome all those challenges. In this paper we describe the key electrical elements in a typical TSI digital system and discuss their impact on overall system performance. We also discuss the system level power integrity analysis for TSI as its power delivery is one of the major engineering challenges.

We present in this paper some design rules to improve the signal integrity (SI) of a package transition. The design rules are based on standard low-pass (LP) filter synthesis methodology. This methodology uses the modeling of the package transition by a network and is valid as long as the through phase shift of the package transition remains sufficiently small. Based on this network approximation, it is possible to add external distributed elements at the package carrier level and lumped elements at the DIE level to build an equivalent low-pass ladder filter. This approach improves significantly the signal integrity properties of the package transition without modifying the package. In some cases the frequency bandwidth for which the return loss (RL) remains higher than 20 dB can be doubled by using this method.Index Terms-Ball grid array (BGA), coplanar waveguide (CPW), microlead frame (MLF), microstripline (MSL).

No abstract