The shift towards reconfigurable systems -hardware and software that adapt themselves to an external contextpromises to unlock unprecedented performance, power consumption, and quality of service. However, reconfiguration imposes several challenges on the design of cyber-physical systems. Current design practices, including software frameworks and programming languages, are ill-prepared for supporting reconfiguration.In this paper, we explore Asynchronous Graph Programming, a programming paradigm and an associated model of computation designed for efficient and automated parallelization across processing elements, efficient reconfiguration (i.e., mapping of computational tasks across processing elements), and combining synchronous and asynchronous I/O handling within the same conceptual programming model. We also introduce an analytical model of parallelization, unlocked by Asynchronous Graph Programming, that can inform reconfiguration strategies.We analyze the implications of our model through an analysis of reconfiguration scenarios given a program's characteristics; our analysis quantifies the benefits of reconfiguring software for higher levels of parallelism, given an amount of data left to process. We also introduce Horde, an open source Asynchronous Graph Programming interpreter, and use it to empirically validate the performance advantage of its automatic parallelism capabilities; in our experiments, automatic parallelization from one to four cores improves average case execution time by a factor of 2 and worst case execution time by a factor of 3.

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Multicore architectures have emerged as an avenue to continue the improvement of software performance even as growth in single-core performance has struggled over the past two decades [1] [2]. However, designing for such systems is a more complex task than for single-core, sequential computing. To effectively utilize multicore systems, designers must devise communication strategies, coordinate dataflow between processing elements in a way that avoids erroneous behaviour such as race conditions, and the software's general architecture must be designed in a way that takes advantage of advancements in hardware architecture [3] [4].In this thesis, we present an architecture and domain-specific language that allows software developers to rapidly prototype hardware architectures, software partitioning, and inter-core communication strategies at design time. We demonstrate an interpreter for this domain-specific language, and use it to illustrate a process of experimenting with inter-core communication and software partitioning strategies.

Modern embedded image processing deployment systems are heterogeneous combinations of general-purpose and specialized processors, custom ASIC accelerators and bespoke hardware accelerators. This paper offers a primer on hardware acceleration of image processing, focusing on embedded, real-time applications. We then survey the landscape of High Level Synthesis technologies that are amenable to the domain, and present our ongoing work on IMP-Lang, a language for early stage design of heterogeneous image processing systems. We show that hardware acceleration is not just a process of converting a piece of computation into an equivalent hardware system: that naive approach offers, in most cases, little benefit. Instead, acceleration must take into account how data is streamed throughout the system, and optimize that streaming accordingly. We show that the choice of tooling plays an important role in the results of acceleration. Different tools, in function of the underlying language paradigm, produce wildly different results across performance, size, and power consumption metrics. Finally, we show that bringing heterogeneous considerations to the language level offers significant advantages to early design estimation, allowing designers to partition their algorithms more efficiently, iterating towards a convergent design that can then be implemented across heterogeneous elements accordingly.

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