No abstract

No abstract

The device characteristics of NAND flash memories with gate sizes from 14 to 32 nm were investigated by using a full three-dimensional technology computer-aided design simulator. Simulation results showed that the threshold voltage and the depletion regions of the floating gate (FG) of the 10-nm NAND flash memories increased with decreasing cell size. The electrical potential of the inter-poly-dielectric (IPD) surface and the tunneling layer surface decreased with increasing depletion region of the FG. The program characteristics of the 10-nm NAND flash memories decreased with decreasing electric potential on the IPD surface and the tunneling oxide surface. The electric field between the floating gate of the target cell and that of the neighboring cell increased with decreasing gate size due to a decrease in the distance between the two neighboring cells. The degradation mechanisms for the program characteristics of 10-nm NAND flash memories were clarified by changing the threshold voltage and the voltage shift.

NAND silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices with double gates fabricated on silicon-on-insulator (SOI) substrates were proposed. The current-voltage characteristics related to the programming operation of the designed nanoscale NAND SONOS flash memory devices on a SOI substrate and on the conventional bulk-Si substrate were simulated and compared in order to investigate device characteristics of the scaled-down memory devices. The simulation results showed that the short channel effect and the subthreshod leakage current for the memory device with a large spacer length were lower than that of the memory device with a small spacer length due to increase of the effective channel length. The device performance of the memory device utilizing the SOI substrate exhibited a smaller subthreshold swing and a larger drain current level in comparison with those on the bulk-Si substrate. These improved electrical characteristices for the SOI devices could be explained by comparing the electric field distribution in a channel region for both devices.

The electrical characteristics of NAND flash memories with a high-k dielectric layer were simulated by using a full three-dimensional technology computer-aided design simulator. The occurrence rate of the errors in the flash memories increases with increasing program/erase cycles. To verify the word line stress effect, electron density in the floating gate of target cell and non-target cell, the drain current in the channel of non-target cell and depletion region of the non-target cell were simulated as a function of program/erase cycle, for various floating gate thicknesses. The electron density in the floating gate became decreased with increasing program/erase cycles. The reliability degradation occured by the increased depletion region at the bottom of the polysilicon floating gate in the continued program/erase cycle situation due to the word line stress. The degradation mechanisms for the program characteristics of 20-nm NAND flash memories were clarified by examining electron density, darin current and depletion region.