No abstract

The commutation principle of Ramirez, Seeger, and Sossa [13] proved in the setting of Euclidean Jordan algebras says that when the sum of a Fréchet differentiable function Θ(x) and a spectral function F (x) is minimized over a spectral set Ω, any local minimizer a operator commutes with the Fréchet derivative Θ ′ (a). In this paper, we extend this result to sets and functions which are (just) invariant under algebra automorphisms. We also consider a similar principle in the setting of normal decomposition systems.

A new, simple closed-form crosstalk model is proposed. The model is based on a lumped configuration but effectively includes the distributed properties of interconnect capacitance and resistance. CMOS device nonlinearity is simply approximated as a linear device. That is, the CMOS gate is modeled as a resistance at the driving port and a capacitance at a driven port. Interconnects are modeled as effective resistances and capacitances to match the distributed transmission behavior. The new model shows excellent agreement with SPICE simulations. Further, while existing models do not support the multiple line crosstalk behaviors, our model can be generalized to multiple lines. That is, unlike previously published work, even if the geometrical structures are not identical, it can accurately predict crosstalk. The model is experimentally verified with 0.35-m CMOS process-based interconnect test structures. The new model can be readily implemented in CAD analysis tools. Thereby, this model can be used to predict the signal integrity for high-speed and high-density VLSI circuit design.

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We explored a new way of designing dynamic logic gates with low temperature polysilicon thin film transistors to increase the speed. The proposed architecture of logic gates utilizes the structural advantage of smaller junction capacitance of thin film transistors. This method effectively blocks leakage of current through the thin film transistors. Furthermore, the number of transistors used in logic gates is reduced thereby reducing power consumption and chip area. Through HSPICE simulation, it is confirmed that the circuit speed is also improved in all logic gates designed.