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In this paper, we present the design and evaluation of a two-phase resonant clock generation and distribution system with layout-extracted inductor parameters in a 0.13µm copper process. The design includes a programmable replenishing clock generator and tunable capacitors that enable the exploration of skew, jitter, and clock amplitude. Our simulation results show that worst-case skew is within 8.5% of clock period in the range of 790MHz to 1.22GHz under a variety of load imbalance conditions. Furthermore, energy dissipation is at least 60% lower than conventional square waveform distribution.

Boost Logic is a charge-recovery circuit family capable of operating at GHz-class frequencies [1]. In this paper, the design and experimental validation of a 1.1GHz Boost Logic test chip is reported. The test chip is fabricated in a 0.13µm CMOS process with an integrated inductor and an on-chip clock generator. This chip is an implementation of a dynamic charge-recovery logic family operating successfully in the GHz regime. Previous charge-recovery circuit implementations with on-chip clock generators have been reported to operate at frequencies no greater than 130MHz [2,3,4]. In addition to fast operation, Boost Logic achieves high energy efficiency due to its (i) balanced clock load, (ii) decoupled logic evaluation and charge-recovery stages, and (ii) absence of diodes. This Boost Logic chip recovers 60% of the energy supplied to it at each clock cycle. Figure 21.5.1 shows a Boost Logic gate. It consists of a dual-rail logic stage that operates in tandem with a charge-recovering boost stage. The logic stage performs functional evaluation and is powered by a dc supply V C = V dd ' -V ss ' = V th , centered at V dd /2. The Boost stage then amplifies the potential difference between out and out to V dd . Figure 21.5.2 illustrates the operation of a Boost inverter. During the boost stage, the header and footer transistors of the logic stage are off, isolating the outputs from the logic rails. As φ(φ) transitions to V ss (V dd ), transistor M3 (M1) discharges (charges) the output node out (out). The output nodes track the power-clocks until their potential difference reaches V th , at which time all transistors in the boost stage are in cut-off and remain so during the subsequent logic stage. As φ falls below V ss ', logic evaluation begins, resolving the output nodes to a potential difference of nearly V th , and as φ crosses V dd ', the boost stage drives the output nodes to the full rail. By relying on resonance to drive the output nodes to a voltage difference V dd , the boost stage efficiently provides a high gate overdrive to fanout logic stages. Although V C = V th , all transistors conduct in the superthreshold linear region due to this high gate overdrive.Fabricated in a 0.13µm 8M (copper, 2 thick) 1.2V CMOS process, this test chip consists of 8 gate chains with a total of 1680 Boost gates comprising AND, OR, XOR and INV. The logic gates and clock generator occupy a total area of 315×320µm 2 . Complementary resonant clocks φ and φ are generated with an Hbridge topology. Pulses a and b at 180˚ are derived from a reference clock and drive the clock generator switches in tandem, periodically replenishing dissipated energy in the system. The frequency f of the reference clock is programmable in the range 700MHz ≤ f ≤ 1.3GHz.The resonant clocks oscillate at the reference frequency f. For efficient operation, f should be near the natural frequency where C is the total capacitance resonated with inductance L. To explore the impact of design trade-offs on energy efficiency, the clock generator is designed with prog...

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An efficient and exhaustive standard-cell abutment verification tool is developed to ensure 100% layout verification coverage of design rule check (DRC) on boundaries created by standard-cell abutment during placement, Vt swap and ECO (engineering change orders). Several case-reduction techniques are presented to remove the redundancy of duplicate abutment. This methodology can achieve one order-of-magnitude reductions in the test area to exercise all boundaries created by all placement permutations in standard cell libraries.