Accurate conversion of wideband multi-GHz analog signals into the digital domain has long been a target of analog-to-digital converter (ADC) developers, driven by applications in radar systems, software radio, medical imaging, and communication systems. Aperture jitter has been a major bottleneck on the way towards higher speeds and better accuracy. Photonic ADCs, which perform sampling using ultra-stable optical pulse trains generated by mode-locked lasers, have been investigated for many years as a promising approach to overcome the jitter problem and bring ADC performance to new levels. This work demonstrates that the photonic approach can deliver on its promise by digitizing a 41 GHz signal with 7.0 effective bits using a photonic ADC built from discrete components. This accuracy corresponds to a timing jitter of 15 fs -a 4-5 times improvement over the performance of the best electronic ADCs which exist today. On the way towards an integrated photonic ADC, a silicon photonic chip with core photonic components was fabricated and used to digitize a 10 GHz signal with 3.5 effective bits. In these experiments, two wavelength channels were implemented, providing the overall sampling rate of 2.1 GSa/s. To show that photonic ADCs with larger channel counts are possible, a dual 20-channel silicon filter bank has been demonstrated. 289-296 (1992). 11. J. Kim, J. Chen, J. Cox, and F. X. Kärtner, "Attosecond-resolution timing jitter characterization of free-running mode-locked lasers using balanced optical cross-correlation," Opt. Lett. microwave signals at 40-GHz with higher than 7-ENOB resolution," Opt. ©2012 Optical Society of America

The phonon-limited mobility of strained Si metal–oxide–semiconductor field-effect transistors (MOSFETs) fabricated on a SiGe substrate is investigated through theoretical calculations including two-dimensional quantization, and compared with the mobility of conventional (unstrained) Si MOSFETs. In order to match both the mobility of unstrained Si MOSFETs and the mobility enhancement in strained Si MOSFETs, it is necessary to increase the coupling of electrons in the two-dimensional gas with intervalley phonons, compared to the values used in conventional models. The mobility enhancement associated with strain in Si is attributed to the following two factors: the suppression of intervalley phonon scattering due to the strain-induced band splitting, and the decrease in the occupancy of the fourfold valleys which exhibit a lower mobility due to the stronger interaction with intervalley phonons. While the decrease in the averaged conductivity mass, caused by the decrease in the occupancy of the fourfold valleys, contributes to the mobility enhancement in bulk strained Si, it is not necessarily adequate to explain the mobility enhancement for two-dimensional electrons in strained Si. This is suggested by the fact that the mobility limited by intravalley acoustic phonon scattering, which is the dominant scattering mechanism, has almost the same value in the two- and the fourfold valleys, because the difference in the conductivity mass is compensated by differences in the inversion-layer thickness and the valley degeneracy.

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Abstract-Deep submicron strained-Si n-MOSFET's were fabricated on strained Si/relaxed Si 0 8 Ge 0 2 heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFET's exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 m) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects.