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Electrical motor fed by voltage source inverters has been known to face transient overvoltage problems caused by the inverter switching operations. With the parallel inverter topology and with the modulation strategy presented in thisstudy, the motor terminal overvoltage can be reduced without any passive filtering. The parallel inverter topology has individual motor leads from each inverter connected at the motor terminals. Modulation strategy for any number of parallel inverters with current balancing is presented. Experimental results are presented for two and three parallel standard industry frequency converters to verify the method.

Frequency converters are used to increase the controllability and efficiency of electric motor drives. Induction motors may experience an insulation failure caused by an overvoltage at the motor terminals. The overvoltage is caused by an impedance mismatch between the motor terminals and the motor cable. Fast pulse rise times compared with the propagation delay in the motor cable will make the terminal voltage exceed the DC link voltage level. Passive filtering techniques for two-level inverters have been developed to cancel out the overvoltage. In this paper, a control method for active du/dt filtering to reduce motor terminal overvoltage is introduced. A filter topology and the basis for setting the filter component values are presented. The size of the passive filter used in this filtering method is smaller than in traditional passive du/dt filters. Functional filtering can be achieved with a smaller filter by controlling the filter output voltage rise time with an accurately timed inverter output voltage. The control of the system is implemented on a field programmable gate array (FPGA) to provide precise gate drive signals with high time resolution.

Active du/dt output filtering is a previously presented method to reduce the variable-speed AC drive cable reflection overvoltages. It uses a passive LC low-pass filter and a pulse pattern from IGBT phase leg to control the filter output voltage slopes. The pulse pattern has to be formed in accordance to the LC filter resonant frequency, and timing errors will show up as additional overshoot at the filter output voltage, eventually reaching motor as well. IGBT phase leg output voltage distortion versus the logiclevel command timing affects the active du/dt filtering performance. This paper evaluates the most relevant error sources in an experimental setup for 22 kW motor with a filter for 200 m cable length. Analysis of the filter under timing errors based on measurement results is shown. The timing distortions have an effect, but in this particular case, the practical implications are not severe as the average overshoot due to timing errors was found to be in range on 10 %.