Hardware architectures for modern hearing aid devices have to provide ultra low power consumption at a small silicon area and moderate computational performance to deal with the continuously growing complexity of hearing aid signal processing. At the same time, they need to remain flexible for future algorithmic changes. These challenging design goals can be achieved by using Application-Specific Instruction-Set Processors (ASIPs), where a baseline architecture is customized to the target class of applications. In this paper, hardware modifications of a generic VLIW-SIMD processor architecture targeting audio processing are described and their influence in area-performance efficiency and power are evaluated. As exemplary hearing aid signal processing application, the evaluated algorithms contain a complex modulated filter bank and a noise reduction algorithm. The proposed architecture requires 2 times less silicon area and a 6 times lower clock frequency than a Tensilica Xtensa LX4 when running the same algorithms under real-time conditions.

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