Bulk silicon device technologies are reaching fundamental scaling limitations. The 28 nm and 22 nm technology nodes have seen the introduction of Ultra-Thin Body and Buried Oxide Fully Depleted SOI (UTBB-FDSOI) devices and FinFETs, respectively. Fully Depleted transistor technologies are mandatory to suppress short channel effects. Today, all major research and development alliances state that the silicon and its Fully Depleted transistor technologies have the potential to address roadmap requirements down to the 10nm node. Innovations will be necessary for lower, more advanced node (under 10nm). Specifications are to continue to ensure a good electrostatic control while providing excellent electrical performance. To meet these demands, several research areas (substrate engineering as well as multiple gate devices and 3D integration) will be involved in integrated circuit fabrication. This paper reports our latest achievements in SOI-type bonded substrates for advanced technology nodes.

To overcome the Fermi-level pinning in III-V metal-oxide-semiconductor capacitors, attention is usually focused on the choice of dielectric and surface chemical treatments prior to oxide deposition. In this work, we examined the influence of the III-V material surface cleaning and the semiconductor growth technique on the electrical properties of metal/Al 2 O 3 /In 0.53 Ga 0.47 As capacitors grown on InP(100) substrates. By means of the capacitance-voltage measurements, we demonstrated that samples do not have the same total oxide charge density depending on the cleaning solution used [(NH 4) 2 S or NH 4 OH] prior to oxide deposition. The determination of the interface trap density revealed that a Fermi-level pinning occurs for samples grown by metalorganic chemical vapor deposition but not for similar samples grown by molecular beam epitaxy. Deep level transient spectroscopy analysis explained the Fermi-level pinning by an additional signal for samples grown by metalorganic chemical vapor deposition, attributed to the tunneling effect of carriers trapped in oxide toward interface states. This work emphasizes that the choice of appropriate oxide and cleaning treatment is not enough to prevent a Fermi-level pinning in III-V metal-oxide-semiconductor capacitors. The semiconductor growth technique needs to be taken into account because it impacts the trapping properties of the oxide.

A photovoltaics conversion efficiency of 46% at 508 suns concentration was recently demonstrated with a four-junction solar cell consisting in a GaAs-based top tandem cell transferred onto an InP-based bottom tandem cell, by means of wafer bonding. We have successfully produced and characterized different InPOS (for InP-On-Substrate) composite substrates, that could advantageously replace fragile and expensive InP bulk wafers for the growth of the bottom tandem cell. The InPOS composite substrates include a thin top InP layer with thickness below 1µm, transferred onto a host substrate using the Smart Cut™ layer transfer technology. We developed InP-On-GaAs, InP-On-Ge and InP-On-Sapphire substrates with surface and crystal qualities similar to the InP bulk ones. A low electrical resistance of 1.4mΩ.cm² was measured along the InP transferred layer and the bonding interface. An epitaxial bottom tandem cell was grown on an InPOS substrate, and the corresponding PL behavior was found identical to that of cells grown on InP bulk reference. The InP-based composite substrates are then very well suited for the fabrication of advanced devices like four-junction solar cells