The complexity of modern digital circuits has increased enormously because of paradigm shift from system-onboard to designs embracing embedded cores-based system-onchips (SOCs). The ensuing intricacy has resulted in a huge challenge in setting up their appropriate fault analysis and testing environment. Though enormous efforts were directed to rapidly test very large-scale integration (VLSI) circuit chips under reasonable cost constraints, with technological advances, new barriers emerged. The subject paper, augmenting earlier works of authors, pertains to developing method that aims to test verify circuit architecture in a hardware-software co-design environment, specifically targeting embedded SOCs. The concept of design-for-testability (DFT) is utilized in this paper, using ModelSim simulation and verification tool, to test simulate the overall design. In earlier works, simulation experience on ISCAS 85 combinational benchmark circuits was provided. In this study, some partial simulation results on ISCAS 89 full scan sequential benchmark circuits are furnished because of space contraint, along with discussion of proposed algorithm and programming basisin a context of ModelSim.