It is shown in the study that Arsenic improves 30% device Idsat variation compared to Ph implantation. SRAM Vccmin value may be improved around 4% too. While it is found that, compared to Ph implantation, Arsenic critically increases junction leakage current, which may account for more than half part of the total off current for high threshold voltage (Vth) device with gate length less than 50nm. The large junction leakage current also leads to 5% device performance degradation and SRAM stand by leakage current (Istby) 15% increasing. Device reliability study exhibits that PMOS negative bias temperature instability (NBTI) performance is deteriorated by Arsenic implantation.

Cell leakage (Istby) reduction of ultra low power (ULP) SRAM with conventional 6T configuration on 65nm low power (LP) technology platform is studied in the paper. Istby components are analyzed and optimized for the leakage reduction by adopting no sleep transistor or other leakage suppression schemes. Gate oxide of cell transistor is grown thicker compared to 65nm LP process to fully suppress the gate oxide leakage contribution. Sub-threshold leakage of the cell transistors are much decreased to lower down both the total Istby and its temperature sensitivity. The 16M ULP SRAM featuring a 0.525μm 2 bit cell size with the proposed technique shows Istby as low as 1.2pA/bit at 1.2V under room temperature and 3.1pA/bit at 85℃. The voltage data retention (VDR) of the ULP SRAM is shown to be 0.7V indicating the feasibility of Istby further reduction by applying low Vdd under stand by mode. Moreover, the ULP process is fully compatible with logic process flow, by adopting several more masks, the above mentioned SRAM can be embedded into standard CMOS flow easily. IntroductionWith the technology keeping scaling down and memory chip occupying more and more the total chip area, SRAM standby leakage (Istby) is becoming a critical concern (1-2). In particular, SRAM Istby control under higher temperature is crucial for certain usages such as automobile electronics. Various circuit design techniques have been reported to reduce Istby focusing on transistor stack, multiple Vth, dynamic Vth or dynamic Vdd schemes (3-7). While the techniques are prominent for Istby controlling, lots of design efforts have to be taken into accounts.In the paper, SRAM Istby in a 65nm LP CMOS logic technology platform is studied. By optimizing cell transistor characteristics and process parameters, Istby is considerably suppressed and so does the Istby to temperature sensitivity. A large ULP SRAM operation voltage window is exhibited, which provides flexibility for SRAM design and the other options for Istby further reduction, through voltage scaling for instance.The paper is organized as follows. Istby components in conventional 6T SRAM is analyzed first for thorough understanding of the Istby leakage sources. Process and device optimization are then described for the ULP purpose. The ULP implementation in a 16M SRAM test chip is then demonstrated, followed by a conclusion in the end.