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This paper proposes a high-efficiency DC–DC converter with charge-recycling gate-voltage swing control with a light load. By achieving a variable gate-voltage swing in a very efficient manner by charge recycling, the power efficiency has been substantially improved due to the lower power consumption and the achieved balance between the switching and conduction losses. A test chip was fabricated using 65-nm CMOS technology. The proposed design reduces the gate-driving loss by up to 87.7% and 47.2% compared to the conventional full-swing and low-swing designs, respectively. The maximum power conversion efficiency was 90.3% when the input and output voltages are 3.3 V and 1.8 V, respectively.

A novel pair-wise staggering transmitter is proposed to reduce the crosstalk noise in single-ended channels at high data rates. This work considers two neighboring channels as a pair, and applies staggering between adjacent pairs. As a result, the peak power of crosstalk-induced jitter (CIJ) and glitch (CIG) are reduced by half, so eye becomes larger for a given noise environment, resulting in higher data rate. A prototype IC adopting the proposed approach was fabricated in a 65 nm CMOS process, whose measurement results indicated that the proposed pair-wise 1/2-UI staggering substantially improved the eye height and width at measured operating range of 4.4 to 6.0 Gbps as compared to the conventional 1/2-UI staggering. In terms of maximum data rate, the proposed approach was valid up to over 6 Gbps, whereas the conventional approach was valid merely up to around 4.8 Gbps, indicating 25% improvement.

PWM buck converters usually use a type-III error amplifier. Since this amplifier has a big capacitor with slow slew rate, they can generate an unintended large overshoot/undershoot at the output when a large load current change occurs. They can also respond slowly by varying the reference voltage. In order to increase battery lifetime, power supplies require a various range of load current and output voltage. PWM buck converter also should have a characteristic of both fast load response and reference tracking. This paper surveys a few recent techniques for reducing the settling time, and discusses their merits and limitations.

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