In this paper, we investigate the threshold voltage disturbance caused by programmed adjacent cells in virtual source/drain (VSD) NAND flash memory device. The fringing field induced by charge in an adjacent memory node inhibits the inversion of virtual source/drain region. So, it increases the threshold voltage of the read cell. This is a drawback for the multi-level cell (MLC) operation. The device simulation and measurement data of fabricated devices show that the disturbance increases as the cell gate length and VSD length decreases. It can be minimized by the electric field concentration induced by the arch shape structure.

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