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In this paper we propose spatial modeling approaches for clustered defects observed using an Integrated Circuit (IC) wafer map. We use the spatial location of each IC chip on the wafer as a covariate for the corresponding defect count listed in the wafer map. Our models are based on a Poisson regression, a negative binomial regression, and Zero-Inflated Poisson (ZIP) regression. Analysis results indicate that yield prediction can be greatly improved by capturing the spatial distribution of defects across the wafer map. In particular, the ZIP model with spatial covariates shows considerable promise as a yield model since it additionally models zero-defective chips. The modeling procedures are tested using a practical example.

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