Summary This paper presents a K‐band high‐gain Class‐A power amplifier (PA) with the two‐way combining approach in GSMC 130‐nm radio frequency (RF) complementary metal oxide semiconductor (RF CMOS). At the input, a slow‐wave transmission‐line transformer (S‐TLT) matching network is proposed for simultaneously realizing the impedance transformation and the single‐ended RF signal to differential conversion. Transmission‐line transformers (TLTs) are employed between the stages for coupling and inter‐stage matching. To improve the output power and efficiency, the placing and routing of the transistor layout are considered carefully for power stages to reduce the interconnecting and overlapping parasitics significantly. The PA has been fabricated and achieved good matching at 25 GHz, power gain of 17.8 dB, saturated output power of 14.9 dBm, output 1‐dB compression point of 12.4 dBm, and power added efficiency of 13.7% at a supply voltage of 1.5 V.

This letter presents a D-band wideband power amplifier (PA) in a 65-nm CMOS process. By pole-tuning technique with T-type network, the PA achieves a flat gain response over a wide bandwidth. The high output power is achieved by combining the output power of two PA cells using a Y-type power combiner (YPC). The fabricated prototype achieves a peak gain of 11.5 dB at 115 GHz with a 3-dB bandwidth of more than 21 GHz and a fractional bandwidth of larger than 17.5%. At the operating frequency of 120 GHz, the saturation output power and the output P 1dB are 13 dBm and 8.7 dBm, respectively. The chip occupies a small silicon area of 0.59 mm 2 including all testing pads with a core size of only 0.32 mm 2 .

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