Resistive-switching random access memory (ReRAM) technologies are nowadays a good candidate to overcome the bottleneck of Von Neumann architectures, taking advantage of their logic-in-memory capability and the ability to mimic biological synapse behavior. Although it has been proven that ReRAMs can memorize multibit information by the storage of multiple internal resistance states, the precise control of the multistates, their nonvolatility, and the cycle-to-cycle reliability are still open challenges. In this study, the analog resistance modulation of Pt/HfO2/Ti/TiN devices is obtained and studied in response to different programming stimuli, linking the electrical response to the internal dynamics of the ReRAM cells. The resistance modulation during RESET operation is explained by the progressive dissolution of the conducting filament, whose switching kinetics is inspected in detail, describing the filament evolution during voltage sweep measurements and under the effect of 1 μs pulses. Exploiting the gradual nature of the RESET process, which is an intrinsic property of our devices, a linear resistance modulation over the wide operating window of 103 is obtained by negative pulse ramping. The intermediate resistance states are characterized by small spatial and temporal variability and stable retention over time. To explore the synaptic long-term plasticity properties, the resistance variation over 102 consecutive depression–potentiation cycles is presented and up to 15 discrete distinguishable states are defined through the evaluation of the maximum step-to-step variability. The linear resistance modulation over a wide resistance window coupled with the stable retention of intermediate states represents a fundamental step forward to enhance HfO2 ReRAM performance in neuromorphic applications.

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The effect of back-end of line (BEOL) process on cell performance and reliability of Phase-Change Memory embedded in a 28nm FD-SOI platform (ePCM) is discussed. The microscopic evolution of the Ge-rich GST alloy during process is the focus of the first part of the paper. A new metric for quantification of active material modifications is introduced to better follow its evolution with process sequence. Ge clustering has been shown to occur during the fabrication, impacting the pristine resistance and the after forming cell performance. Two different BEOL processes are then benchmarked in terms of key performance. An optimized process is identified, and an extensive electrical characterization of array performance and reliability is done on the full 16MB chip. The optimized BEOL process results in a memory cell fully compatible with the requirements for demanding automotive applications.

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