The fast development of the Internet of things (IoT) promises to deliver convenience to human life. However, a huge amount of the data is constantly generated, transmitted, processed, and stored, posing significant security challenges. The currently available security protocols and encryption techniques are mostly based on software algorithms and pseudorandom number generators that are vulnerable to attacks. A true random number generator (TRNG) based on devices using stochastically physical phenomena has been proposed for auditory data encryption and trusted communication. In the current study, a Bi2O2Se-based memristive TRNG is demonstrated for security applications. Compared with traditional metal–insulator–metal based memristors, or other two-dimensional material-based memristors, the Bi2O2Se layer as electrode with non-van der Waals interface, high carrier mobility, air stability, extreme low thermal conductivity, as well as vertical surface resistive switching shows intrinsic stochasticity and complexity in a memristive true analogue/digital random number generation. Moreover, those analogue/digital random number generation processes are proved to be resilient for machine learning prediction.

In the past few decades, driven by the increasing demands in the biomedical field aiming to cure neurological diseases and improve the quality of daily lives of the patients, researchers began to take advantage of the semiconductor technology to develop miniaturized and power-efficient chips for implantable applications. The emergence of the integrated circuits for neural prosthesis improves the treatment process of epilepsy, hearing loss, retinal damage, and other neurological diseases, which brings benefits to many patients. However, considering the safety and accuracy in the neural prosthesis process, there are many research directions. In the process of chip design, designers need to carefully analyze various parameters, and investigate different design techniques. This article presents the advances in neural recording and stimulation integrated circuits, including (1) a brief introduction of the basics of neural prosthesis circuits and the repair process in the bionic neural link, (2) a systematic introduction of the basic architecture and the latest technology of neural recording and stimulation integrated circuits, (3) a summary of the key issues of neural recording and stimulation integrated circuits, and (4) a discussion about the considerations of neural recording and stimulation circuit architecture selection and a discussion of future trends. The overview would help the designers to understand the latest performances in many aspects and to meet the design requirements better.

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This paper presents chip implementation of the integrated neural recording and stimulation system with stimulation-induced artifact suppression. The implemented chip consists of low-power neural recording circuits, stimulation circuits, and action potential detection circuits. These circuits constitute a closed-loop simultaneous neural recording and stimulation system for biomedical devices, and a proposed artifact suppression technique is used in the system. Moreover, this paper also presents the measurement and experiment results of the implemented 4-to-4 channel neural recording and stimulation chip with 0.18 µm CMOS technology. The function and efficacy of simultaneous neural recording and stimulation is validated in both in vivo and animal experiments.

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