With fabrication technology reaching nanolevels, systems are becoming more prone to manufacturing defects with higher susceptibility to soft errors. Soft errors caused by particles strike in combinational parts of digital circuits are a major concern in the design of reliable circuits. Several techniques have been presented to protect combinational logic and reduce the overall circuit Soft Error Rate (SER). Such techniques, however, typically come at the cost of significant area and performance overheads. A comprehensive review on the soft error generation and different fault tolerance techniques used, are presented in this study. After the overall concepts and general ideas are presented, representative works as well as new progress in the techniques are covered and discussed in detail.