This paper discuss designing of low power, high-speed 10-Transistor (10T) SRAM and analysis of SRAM cell in Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and FinFET technology. MOSFET is used widely in many areas, but below 40 nm technology control of channel region becomes extremely difficult. So there is a necessity for new innovative technology which allows designers to design below 40nm technology and can offer excellent control over gate thus reducing short channel effects. The designing of SRAM is analyzed using TANNER EDA tool and Microwind.