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Internet of things (IoTs) enabled cyber-physical systems is a system that provides communication between physical devices and cyber environment. They run independently without any user interaction. Because the IoT devices are vulnerable to a variety of attacks, security is a noteworthy factor in the development process during communication. To improve secure communication with minimum time consumption, a novel technique called jackknife regressive Schmidt Samoa cryptography-based deep artificial structure learning (JRSSC-DASL) is introduced. Initially, the data is monitored by IoT devices and is collected from the dataset. The proposed deep artificial structure learning technique trains the gathered data with multiple layers. Then, the collected data is analysed in the first hidden layer with the help of the jackknife regression function by learning the feature and it classifies the data with higher accuracy. The classified data is sent to the next hidden layer where encryption is performed using Schmidt Samoa (SS) encryption algorithm. Then, the encrypted data is sent to the cloud server where the decryption is performed using the SS decryption algorithm. The cloud server obtains the original data and it is stored in their database for further processing. This process enhances the security of data communication and achieves high data confidentiality with less processing time. Experimental estimation is performed on the factors such as classification accuracy, confidentiality rate, processing time and memory usage to the number of data sensed from IoT device. Conferred results reveal that the proposed JRSSC-DASL technique has high confidentiality rate and minimum processing time as well as memory usage when compared to state-of-the-art methods. This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

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<p>Cryptographic algorithms need infrastructure for testing them against security attacks. Normally many methods are proposed for testing these cryptographic primitives. Normal designs cannot be applied to all types of cryptographic chips. Usually build in self test is applied for the intellectual property chips for testing them. But it suffers from many problems such as side channel attack, backholes, high area overhead, etc.., to overcome all these drawbacks test wrapper is designed and tested using NIOS II economy soft core processor.  NIOS II is utilized as the soft core processor and cryptographic algorithms are executed. RTL view of these cryptographic circuits is described. Synthesis result shows the chip planner view of the circuits and the area required for the logic elements. NIOS II soft-core processors perform well for testing the cryptographic algorithms. Results with respects to area optimization, memory and speed are discussed. The logic components required for design using NIOS II is optimized. Memory required is also less compare to other processors. Area required is optimized using NIOS II processor and it is flexible for design of complex circuits.</p>