A method has been developed for the manufacture of a "three-dimensional" electrode array geometry for chronic intracortical stimulation. This silicon based array consists of a 4.2 x 4.2 x 0.12 mm thick monocrystalline substrate, from which project 100 conductive, silicon needles sharpened to facilitate cortical penetration. Each needle is electrically isolated from the other needles, and is about 0.09 mm thick at its base and 1.5 mm long. The sharpened end of each needle is coated with platinum to facilitate charge transfer into neural tissue. The following manufacturing processes were used to create this array. 1) Thermomigration of 100 aluminum pads through an n-type silicon block. This creates trails of highly conductive p+ silicon isolated from each other by opposing pn junctions. 2) A combination of mechanical and chemical micromachining which creates individual penetrating needles of the p+ silicon trails. 3) Metal deposition to create active electrode areas and electrical contact pads. 4) Array encapsulation with polyimide. The geometrical, mechanical, and electrical properties of these arrays should make them well suited as interfaces to cortical tissue.

A new manufacturing technique has been developed for creating silicon-based, penetrating electrode arrays intended for implantation into cerebral cortex. The arrays consist of a 4.2 mm x 4.2 mm glass/silicon composite base, from which project 100 silicon needle-type electrodes in a 10 x 10 array. Each needle is approximately 1,500 microns long, 80 microns in diameter at the base, and tapers to a sharp point at the metalized tip. The technique used to manufacture these arrays differs from our previous method in that a glass dielectric, rather than a p-n-p junction, provides electrical isolation between the individual electrodes in the array. The new electrode arrays exhibit superior electrical properties to those described previously. We have measured interelectrode impedances of at least 10(13) omega, and interelectrode capacitances of approximately 50 fF for the new arrays. In this paper, we describe the manufacturing techniques used to create the arrays, focusing on the dielectric isolation technique, and discuss the electrical and mechanical characteristics of these arrays.

A CMOS very large scale integration (VLSI) chip has been designed and built to implement a scheme developed for multiplexing/demultiplexing the signals required to operate an intracortical stimulating electrode array. Because the use of radio telemetry in a proposed system utilizing this chip may impose limits upon the rate of data transmission to the chip, the scheme described herein was used to reduce the amount of digital information which must be sent to control a large quantity (up to several hundred) of stimulating electrodes. By incorporating multiple current sources on chip, many channels may be stimulated simultaneously. By incorporating on-chip timers, control over pulse timing is assigned to the chip, reducing by up to fourfold the amount of control data which must be sent. By incorporating on-chip RAM, information associated with the desired stimulus amplitude and pulse timing can be stored on chip. In this manner, it is necessary to send control information to the chip only when the information changes, rather than at the stimulus repeat rate for each channel. This further reduces the data rate by a factor of five to ten times or more. The architecture described here, implemented as an eight-channel stimulator, is scalable to a 625-channel stimulator while keeping data transmission rates under 2 Mbps.

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