The main challenge in MOSFET minituarization is to form an ultra-shallow source/drain (S/D) junction with high doping concentration gradient, which requires an intricate S/D and channel engineering. Junctionless MOSFET configuration is an alternative solution for this issue as the junction and doping gradients is totally eliminated. A process simulation has been developed to investigate the impact of junctionless configuration on the double-gate vertical MOSFET. The result proves that the performance of junctionless double-gate vertical MOSFETs (JLDGVM) are superior to the conventional junctioned double-gate vertical MOSFETs (JDGVM). The results reveal that the drain current (ID) of the n-JLVDGM and p-JLVDGM could be tremendously enhanced by 57% and 60% respectively as the junctionless configuration was applied to the double-gate vertical MOSFET. In addition, junctionless devices also exhibit larger ION/IOFF ratio and smaller subthreshold slope compared to the junction devices, implying that the junctionless devices have better power consumption and faster switching capability.
This paper presents a study of optimizing input process parameters on leakage current (IOFF) in silicon-on-insulator (SOI) Vertical Double-Gate [1] Metal Oxide Field-Effect-Transistor (MOSFET) by using L36 Taguchi method. The performance of SOI Vertical DG-MOSFET device is evaluated in terms of its lowest leakage current (IOFF) value. An orthogonal array [2], main effects, signal-to-noise ratio (SNR) and analysis of variance (ANOVA) are utilized in order to analyze the effect of input process parameter variation on leakage current (IOFF). Based on the results, the minimum leakage current ((IOFF) of SOI Vertical DG-MOSFET is observed to be 0.009 nA/µm or 9 ρA/µm while keeping the drive current (ION) value at 434 µA/µm. Both the drive current (ION) and leakage current (IOFF) values yield a higher ION/IOFF ratio (48.22 x 10 6 ) for low power consumption application. Meanwhile, polysilicon doping tilt angle and polysilicon doping energy are recognized as the most dominant factors with each of the contributing factor effects percentage of 59% and 25%.
The junctionless MOSFET architectures appear to be attractive in realizing the Moore’s law prediction. In this paper, a comprehensive 2-D simulation on junctionless vertical double-gate MOSFET (JLDGVM) under geometric and process consideration was introduced in order to obtain excellent electrical characteristics. Geometrical designs such as channel length (Lch) and pillar thickness (Tp) were considered and the impact on the electrical performance was analyzed. The influence of doping concentration and metal gate work function (WF) were further investigated for achieving better performance. The results show that the shorter Lch can boost the drain current (ID) of n-JLDGVM and p-JLDGVM by approximately 68% and 70% respectively. The ID of the n-JLVDGM and p-JLVDGM could possibly boost up to 42% and 78% respectively as the Tp is scaled down from 11nm to 8nm. The channel doping (Nch) is also a critical parameter, affecting the electrical performance of both n-JLDGVM and p-JLDGVM in which 15% and 39% improvements are observed in their respective ID as the concentration level is increased from 1E18 to 9E18 atom/cm3. In addition, the adjustment of threshold voltage can be realized by varying the metal WF.
<p>This paper presents an investigation on properties of Double Gate FinFET (DGFinFET) and impact of physical properties of FinFET towards short channel effects (SCEs) for 30 nm device, where depletion-layer widths of the source-drain corresponds to the channel length aside from constant fin height (HFIN) and the fin thickness (TFIN). Virtual fabrication process of 3-dimensional (3D) design is applied throughout the study and its electrical characterization is employed and substantial is shown towards the FinFET design whereby in terms of the ratio of drive current against the leakage current (ION/IOFF ratio) at 563138.35 compared to prediction made by the International Technology Roadmap Semiconductor (ITRS) 2013. Conclusively, the incremental in ratio has fulfilled the desired in incremental on the drive current as well as reductions of the leakage current. Threshold voltage (VTH) meanwhile has also achieved the nominal requirement predicted by the International Technology Roadmap Semiconductor (ITRS) 2013 for which is at 0.676±12.7% V. The ION , IOFF and VTH obtained from the device has proved to meet the minimum requirement by ITRS 2013 for low performance Multi-Gate technology.</p>
Application of strained channel in Metal-oxide-semiconductor Field Effect Transistors (MOSFET) technology influences the electrical properties due to the significant changes in the energy band structure of silicon lattices. Thus, in this paper, a comprehensive analysis is conducted to investigate the impact of strained channel towards several electrical properties of junctionless double-gate MOSFET. The comparative analysis is carried out by simulating two different sets of device structure which are JLDGM device (without strain) and junctionless double-gate strained MOSFET (JLDGSM) device. The results show that the strained channel has improved the on-state current (ION), on-off ratio, transconductance (gm) and transconductance generation factor (TGF) by approximately 58 %, 98%, 98%, and 44% respectively. The significant improvement is mainly attributed to the presence of biaxial strain boosting the electron mobility in the channel. The intrinsic gate delay (τint) has significantly reduced by approximately 52% as the strained channel is applied. Since the variation of intrinsic gate capacitances (Cint) is very minimal (4%) as the strained channel is applied, the gate delay is dominantly governed by the drain current. However, the application of strain channel has increased the dynamic power dissipation (Pdyn) for approximately 19% mainly due to slightly increased intrinsic gate capacitances.
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