PurposeAims to present a finite element analysis based methodology for estimating the characteristic fatigue life of a solder joint interconnect under accelerated temperature cycling to predict the reliability performance of a flip chip package.Design/methodology/approachThe method uses the ANSYSTM finite element analysis tool along with Anand's viscoplastic constitutive law. Darveaux's crack growth rate model was applied to calculate solder joint characteristic life using simulated viscoplastic strain energy density results at the package substrate and printed circuit board solder joints. Two package configurations are evaluated with the above methodology, with the first being a simplified flip chip model and the second being a detailed flip chip model. Each of these configurations is subjected to two accelerated temperature cycling tests.FindingsGenerally, the results indicate that the solder joint at the corner end of the package tends to fail first. The characteristic lives of solder joint at the package ball/board interface are 24‐46 percent higher than the characteristic lives of solder joint at the package ball/substrate interface. This means that the interface between the solder ball and substrate will fail first before the interface between the solder ball and the board.Originality/valueDemonstrates that genetic algorithms can be used as tools to predict possible package dimensional values for given constraints on solder joint life.

In recent fast pace smart manufacturing environment, the short production runs (SPR) control charts offer a higher degree of flexibility compared to the traditional control charts. This is due to Phase I data collection not needed for SPR control charts and this eases practitioners in estimating the parameters and setting up the control charts. This paper proposes the methods to optimally design the SPR S‐chart and SPR S2‐EWMA control chart for process variance monitoring in terms of truncated average run length (TARL), truncated standard deviation of the run length (TSDRL), and expected truncated average run length (ETARL) performance measures. The optimal parameters in minimizing the TARL and ETARL values for SPR S2‐EWMA control chart are presented. The control chart performances are compared between both the SPR S‐chart and SPR S2‐EWMA control charts. Results show that SPR S2‐EWMA control chart has a higher chart sensitivity and it triggers the out‐of‐control signal faster than the SPR S‐chart. An illustration using the real electronic manufacturing industry data is given in this paper to explain the implementation of the SPR S‐chart and SPR S2‐EWMA control chart.