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Abstract-This paper describes a bidirectional, differential, 16 Gb/s per link memory interface that includes a Controller and an emulated DRAM physical interface (PHY) designed in 65 nm CMOS. To achieve high data rate, the interface employs the following technology ingredients: asymmetric equalization, asymmetric timing calibration, asymmetric link margining, inductor based (LC) PLLs, multi-phase error correction, and a data dependent regulator. At 16 Gb/s, this interface achieves a unit-interval to inverter FO4 ratio of 2.8 (Controller) and 1.4 (DRAM) and operates in a channel with 15 dB loss at Nyquist. Under such bandwidth limitations on and off chip, the Controller and DRAM PHYs consume 13 mW/Gb/s and 8 mW/Gb/s, respectively. Using PRBS 2 11 1, the link achieves a timing margin of 0.19 UI at a BER of 1e-12 for both read and write operations.

An 8-channel 10-bit pipeline analog-to-digital converter, designed for use in an integrated three-dimensional ultrasound imaging system, has been implemented in a 0.25-m CMOS technology. Two parallel multiplexing sample-and-hold stages are employed to multiplex a total of eight adjacent ultrasound channels, each sampled at 20 MHz. The sampled and multiplexed signals are fed into two parallel time-interleaved pipeline paths, each operating at 80 MHz. The two parallel pipelines are subsequently multiplexed into a single pipeline operating at 160 MHz to conserve area and reduce complexity. An experimental prototype of the proposed architecture occupies less than 4 mm 2 of active silicon area and shows a peak signal-to-noise-plus-distortion ratio more than 54 dB for a 2.1-MHz input signal, while dissipating only 20 mW of analog power per input channel from a 2.5-V supply.