Semiconductor packaging is trending towards a miniaturisation in size but an increase in functionality. Hence, the thickness of the silicon wafer has decreased dramatically with a concern on the possible degradation of the strength of the thinned wafer. In this paper, 3-point bend (3PB) on bare silicon is selected as the preferred silicon break strength (SBS) test methodology due to its setup effectiveness and subsequent application in the prediction study. This experimental testing study focused on evaluating the SBS from different thickness ranges. The study was then followed by evaluating the influence of a possible impact from flaw creation with laser marking on silicon surfaces. The results show that the SBS is consistent although with significant differences in the silicon thickness ranges. It is also revealed that the onset breaking load may not be a suitable metric and could be over sensitive on gauging the SBS comparison. The flaw creation from the engraving process revealed a significant drop of 75% SBS although with an approximate depth removal of <10% from the total thickness. The consistence failure mode is clearly visible and this left the silicon very vulnerable to catastrophic failure. This indicates that extra care is needed on ultra-thin silicon during the assembly process as fractures may happen even before any reliability stress test is conducted. Furthermore, the completion of the package level 3PB failure mode verification has helped to demonstrate that an SBS study can be conducted with a simplified bare silicon level testing. In short, the study with this simplified 3PB has successfully proven its usefulness in SBS estimation. The observed ultra-thin silicon SBS has degraded and strongly depended on the critical flaws especially from the surface defect and impact from the assembly handling.