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A very low voltage (1.5V) read operation and low power consumption EPROM has been integrated into a 0.8um CMOS process for consumer oriented ASIC applications. These characteristics are accomplished by a new dynamic read circuit which consists of a flipflop sense amplifier and a word-line booster circuit. High speed read cycle time 15011s at 2V and wide operating voltage range from 1.5V to 6V are achieved. This circuit technology is applicable to Flash-EEPROM.An 8-bit microcontroller with 60K-byte EPROM was developed using this technology. It i s suitable for battery operating system supplied minimum voltage of 1.8V by two nickel -cadmium batteries.

This paper presents a new test and characterization scheme for 10+ GHz low jitter wide band PLL in 90 nm partially depleted (PD) Silicon-On-Insulator (SOI) CMOS technology. We measure the frequency range of VCOs without adding any devices for test between charge-pump (CP) and voltage-controlled oscillator (VCO). That test scheme gives us the intermediate frequency of VCO as well as the maximum and the minimum frequency. This paper also describes circuitry to observe the duty cycle of 4.2GHz clock directly on a wafer probe station, including a method to verify the measured duty cycle.