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Chip packaging technology with circuit-under-pad (CUP) structure is developed for porous SiOCH (k=2.55) /Cu dual-damascene interconnects.Wire bonding damage is mainly improved by the pad structure. For molding process, it is important to decrease the coefficient of thermal expansion (CTE) of the molding compounds. Combining the stress controls in these packaging processes with the contrived low-k deposition, high performance 65nm-node, ULSI chips are fumished in low-cost QFP with a conventional wire bonding.

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