The authors investigated the etching of grooves in low-k in Cu technology. Correlation between the line edge roughness ͑LER͒ and the time-dependent dielectric breakdown ͑TDDB͒ reliability for 100 nm pitch Cu interconnects was investigated. They controlled LER by using various gases to etch multilayer photoresist. CF 3 I gas was found to reduce LER better than conventional gases such as CF 4 and CHF 3 because CF 3 I has higher etching selectivity of photoresist against spin-on glass film. The LER did not affect measures of electrical performance such as wiring resistance, capacitance, and leakage current, but did affect TDDB lifetime because, according to their simulation, the electric field was strongly enhanced at curvatures in the interconnects. The maximum electric field ͑E max ͒ was also determined to evaluate the effect of LER on TDDB lifetime. All their results show that CF 3 I etching is promising for creating reliable Cu interconnects with smaller pitches.

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Copper (Cu)/low-k interconnects were fabricated using novel Cu diffusion-barrier SiC films deposited with a novel precursor, 1,1-divinylsilacyclopentane (DVScP). At 46% overetching time, the yield of the via-contact with the dielectric barrier of conventional SiC films was seriously reduced, while that of the novel SiC films was hardly reduced. By using the novel SiC films, the thickness of diffusion barriers was successfully reduced to 15 nm, matching the 32 nm node and beyond. By using the novel SiC films, the dielectric constant of the barrier films was decreased and their thickness was reduced with no yield reduction of the via-contact. As a result, the product of wiring resistance and capacitance (RC product) was reduced by 11.4%. The time-dependent dielectric breakdown (TDDB) lifetime of Cu interconnects with the SiC films was similar to that with the SiCO films. #

Extreme ultraviolet lithography (EUVL) is moving into the phase of the evaluation of integration for device fabrication. This paper describes its applicability to the fabrication of back-end-of-line (BEOL) test chips with a feature size of hp 35 nm, which corresponds to the 19-nm logic node. The chips were used to evaluate two-level dual damascene interconnects made with low-k film and Cu. The key factors needed for successful fabrication are a durable multi-stack resist process, accurate critical dimension (CD) control, and usable overlay accuracy for the lithography process. A multi-stack resist process employing 70-nm-thick resist and 25-nm-thick SOG was used on the Metal-1 (M1) and Metal-2 (M2) layers. The resist thickness for the Via-1 (V1) layer was 80 nm. To obtain an accurate CD, we employed rulebased corrections involving mask CD bias to compensate for flare variation, mask shadowing effects, and optical proximity effects. With these corrections, the CD variation for various 35-nm trench and via patterns was about ± 1 nm. The total overlay accuracy (|mean| ± 3σ) for V1 to M1 and M2 to V1 was below 12 nm. Electrical tests indicate that the uses of Ru barrier metal and scalable porous silica are keys to obtaining operational devices. The evaluation of a BEOL test chip revealed that EUVL is applicable to the fabrication of hp-35-nm interconnects and that device development can be accelerated.

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